Semiconductor device
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorsKiyoshi Kato, Tatsuya Onuki
Life of this patent
Estimating the term…
Abstract
A semiconductor device with a novel structure in which storage capacity needed for holding data can be secured even with miniaturized elements is provided. In the semiconductor device, electrodes of a capacitor are an electrode provided in the same layer as a gate of a transistor and an electrode provided in the same layer as a source and a drain of the transistor. Further, a layer in which the gate of the transistor is provided and a wiring layer connecting the gates of the transistors in a plurality of memories are provided in different layers. With this structure, parasitic capacitance formed around the gate of the transistor can be reduced, and the capacitor can be formed in a larger area.
Claims14
A semiconductor device comprising:
- a plurality of memories, each of the plurality of memories comprising:
- a volatile memory including a first data holding portion;
- and
- a nonvolatile memory including a second data holding portion,
- wherein:
- the second data holding portion includes a first transistor and a first capacitor,
- a first electrode of the first transistor is electrically connected to the first data holding portion,
- a second electrode of the first transistor is electrically connected to a first electrode of the first capacitor,
- the first electrode of the first capacitor and the first electrode of the first transistor are on a same layer, and
- a second electrode of the first capacitor and a gate of the first transistor are on a same layer;
- and
- a first wiring between the plurality of memories,
- wherein:
- the first wiring is configured to electrically connect gates of first transistors of the plurality of memories, and
- a layer in which the first wiring is provided and a layer in which the gate of the first transistor is provided are different.
A semiconductor device comprising:
- a plurality of memories, each of the plurality of memories comprising:
- a volatile memory including a first data holding portion and a second data holding portion;
- and
- a nonvolatile memory including a third data holding portion and a fourth data holding portion,
- wherein:
- the third data holding portion includes a first transistor and a first capacitor,
- the fourth data holding portion includes a second transistor and a second capacitor,
- a first electrode of the first transistor is electrically connected to the first data holding portion,
- a second electrode of the first transistor is electrically connected to a first electrode of the first capacitor,
- a first electrode of the second transistor is electrically connected to the second data holding portion,
- a second electrode of the second transistor is electrically connected to a first electrode of the second capacitor,
- the first electrode of the first capacitor and the first electrode of the first transistor are on a same layer, and
- a second electrode of the first capacitor, a second electrode of the second capacitor, a gate of the first transistor, and a gate of the second transistor are on a same layer;
- and
- a first wiring between the plurality of memories,
- wherein:
- the first wiring is configured to electrically connect the gate of the first transistor and the gate of the second transistor, and
- a layer in which the first wiring is provided and a layer in which the gate of the first transistor and the gate of the second transistor are provided are different.
Dependencies are inferred from the claim text.