Apparatus for high speed ROM cells
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorJhon-Jhy Liaw
Life of this patent
Estimating the term…
Abstract
A ROM cell comprises a first first-level contact formed on a first active region of a transistor of a memory cell, a second first-level contact formed on a second active region of the transistor of the memory cell, wherein the second first-level contact is coupled to a first VSS line and a second VSS line formed in a first interconnect layer, wherein the second VSS line is electrically coupled to the first VSS line, and wherein the second VSS line is of a direction orthogonal to a direction of the first VSS line. The ROM cell further comprises a first bit line formed in the first interconnect layer, wherein the first bit line is formed in parallel with the second VSS line and a second bit line formed in the first interconnect layer, wherein the second bit line is formed in parallel with the second VSS line.
Claims20
A device comprising:
- a fin structure over a substrate;
- a gate wrapping the fin structure around three sides of the fin structure;
- a first VSS line in a contact layer overlying the substrate;
- a first bit line in a first interconnect layer overlying the contact layer;
- a second bit line in the first interconnect layer, wherein the second bit line is in parallel with the first bit line;
- a word line in a second interconnect layer overlying the first interconnect layer;
- and
- a word line strap structure comprising:
- a gate contact in the contact layer;
- a first via in the first interconnect layer:
- a first metal line in the first interconnect layer, wherein the first metal line is over the first via;
- and
- a second via in the second interconnect layer, wherein the word line is over the second via.
A memory cell comprising:
- a memory transistor comprising a drain, a source, a gate, and a channel coupled between the drain and the source;
- a first VSS line in a contact layer overlying a substrate;
- a first bit line in a first interconnect layer overlying the contact layer;
- a second bit line in the first interconnect layer, wherein the second bit line is in parallel with the first bit line;
- a second VSS line in the first interconnect layer, wherein the second VSS line is in parallel with first bit line;
- a word line in a second interconnect layer overlying the first interconnect layer;
- a third VSS line in the second interconnect layer, wherein the third VSS line is in parallel with the word line;
- and
- a word line strap structure coupled between the gate and the word line.
An apparatus comprising:
- a plurality of interconnect structures over a substrate;
- a gate in a contact layer over the substrate;
- a first VSS line in the contact layer;
- a first bit line in a first interconnect layer over the contact layer;
- a second bit line in the first interconnect layer, wherein the second bit line is in parallel with the first bit line;
- a second VSS line in the first interconnect layer, wherein the second VSS line is orthogonal to the first VSS line;
- a word line in a second interconnect layer over the first interconnect layer;
- a third VSS line in the second interconnect layer, wherein the third VSS line is in parallel with the word line;
- and
- a word line strap structure coupled between the gate and the word line.
Dependencies are inferred from the claim text.