Non-volatile memory device

A non-volatile memory device comprising one or more memory cells, wherein

• each of the memory cells comprises a memory transistor, a first selection transistor, and a second selection transistor, and a source and a drain of the memory transistor, a source or a drain of the first selection transistor, and a source or a drain of the second selection transistor are electrically connected to one another to form an internal node of each memory cell,
• the memory transistor comprises a transistor structure having a gate electrode, a source region, a drain region, and a channel region, each region being composed a metal oxide semiconductor,
• the memory transistor holds in a non-volatile manner any one of a first state in which a current/voltage characteristic between the source region and the drain region changes depending on a voltage application state of the gate electrode and a second state in which a current/voltage characteristic between the source region and the drain region indicates an ohmic resistance characteristic regardless of a voltage application state of the gate electrode, and
• the memory transistor has a state transition characteristic which transits from the first state to the second state depending on a current flowing between the source and the drain,
• the non-volatile memory device is configured so that at a writing operation time of transiting the memory transistor from the first state to the second state, a conducting state is set between the source and the drain of the first selection transistor, a non-conducting state is set between the source and the drain of the second selection transistor, and a writing current flows in the memory transistor and the first selection transistor, and
• the non-volatile memory device is configured so that at a reading operation time of detecting whether the memory transistor is in the first state or the second state, a non-conducting state is set between the source and the drain of the first selection transistor, a conducting state is set between the source and the drain of the second selection transistor, and a reading voltage is applied between the source and the drain of the memory transistor.