Semiconductor packages and methods of packaging semiconductor devices
AssigneeUTAC Headquarters Pte. Ltd.
InventorsKriangsak Sae Le, Chee Kay Chow
Life of this patent
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AssigneeUTAC Headquarters Pte. Ltd.
InventorsKriangsak Sae Le, Chee Kay Chow
Estimating the term…
A method of forming semiconductor assemblies is disclosed. The method includes providing an interposer with through interposer vias. The interposer includes first and second surfaces. The through interposer vias extend from the first surface to the second surface of the interposer. The interposer with the through interposer vias enable attachment and electrical coupling of a die having very fine contact pitch to an external device having relatively larger contact pitch. At least a first die is mounted on at least one die attach region on the first surface of the interposer. The first die comprises a first surface with first conductive contacts thereon. The interposer comprises material with CTE similar to that of the first die. The first conductive contacts of the first die are coupled to the through interposer vias on the first surface of the interposer. A bonding process which does not require a reflow process is performed to form connections between the first die and interposer.
A method of forming semiconductor assemblies comprising:
The method of 9 wherein the underfills are provided prior to mounting the first and second dies.
A semiconductor assembly comprising:
Dependencies are inferred from the claim text.