Conductive bump, semiconductor chip and stacked semiconductor package using the same

A stacked semiconductor package comprising:

• a plurality of semiconductor chips each including a semiconductor substrate having a first surface and a second surface which faces away from the first surface, a through via formed to pass through the first surface and the second surface of the semiconductor substrate, an upper bump having a step member formed on a portion of the through via and having the shape of a hemisphere, and a conductive member formed directly on the through via and the step member to have an inclined surface, and a lower bump formed on the second surface of the semiconductor substrate and electrically connected with the through via,
• wherein the plurality of semiconductor chips are stacked such that the upper bump of a lower semiconductor chip which is disposed at the lower among any two stacked semiconductor chips connects with the lower bump of an upper semiconductor chip which is disposed at the upper among any two stacked semiconductor chips.