Patterning approach for improved via landing profile
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChih-Yuan Ting, Chung-Wen Wu
Life of this patent
Estimating the term…
Loading patent…
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChih-Yuan Ting, Chung-Wen Wu
Estimating the term…
The present disclosure is directed to a semiconductor structure and a method of manufacturing a semiconductor structure in which a spacer element is formed adjacent to a metal body embedded in a first dielectric layer of a first interconnect layer. A via which is misaligned relative to an edge of the metal body is formed in a second dielectric material in second interconnect layer disposed over the first interconnect layer and filled with a conductive material which is electrically coupled to the metal body. The method allows for formation of an interconnect structure without encountering the various problems presented by via substructure defects in the dielectric material of the first interconnect layer, as well as eliminating conventional gap-fill metallization issues.
A semiconductor structure, comprising:
A semiconductor structure, comprising:
A semiconductor structure, comprising:
Dependencies are inferred from the claim text.