Semiconductor device with semiconductor chip and wiring layers
AssigneeRenesas Electronics Corporation
InventorsShuuichi Kariyazaki, Ryuichi Oikawa
Life of this patent
Estimating the term…
Loading patent…
AssigneeRenesas Electronics Corporation
InventorsShuuichi Kariyazaki, Ryuichi Oikawa
Estimating the term…
To improve noise immunity of a semiconductor device. A wiring substrate of a semiconductor device includes a first wiring layer where a wire is formed to which signals are sent, and a second wiring layer that is mounted adjacent to the upper layer or the lower layer of the first wiring layer. The second wiring layer includes a conductor plane where an aperture section is formed at a position overlapped with a portion of the wire 23 in the thickness direction, and a conductor pattern that is mounted within the aperture section of the conductor plane. The conductor pattern includes a main pattern section (mesh pattern section) that is isolated from the conductor plane, and plural coupling sections that couple the main pattern section and the conductor plane.
A semiconductor device comprising:
A semiconductor device comprising:
Dependencies are inferred from the claim text.