Methods of forming parallel wires of different metal materials through double patterning and fill techniques

An integrated circuit, comprising:

• a first dielectric layer including a surface;
• a plurality of first trenches defined in said dielectric layer surface;
• a plurality of first wires, wherein each of said first wires are formed in each of said first trenches, wherein said first wires comprise a first material having a first bulk resistivity;
• a plurality of second trenches defined in said dielectric layer surface;
• and
• a plurality of second wires;
• wherein:
• each of said second wires are formed in each of said second trenches;
• said second wires comprise a second material having a second bulk resistivity;
• said first bulk resistivity and said second bulk resistivity are different;
• and
• the integrated circuit further comprises a hardmask layer comprising a first hardmask disposed over said first dielectric layer and a second hardmask disposed over said first material.

An integrated circuit comprising:

• a dielectric layer;
• a first set of wires formed within the dielectric layer, the first set of wires comprising a first conductive material;
• and
• a second set of wires formed within the dielectric layer, the second set of wires comprising a second conductive material different than the first conductive material;
• wherein:
• the first set of wires alternates with the second set of wires such that each wire of the first set is only adjacent to wires of the second set, and wherein each wire of the second set is only adjacent to wires of the first set;
• and
• the integrated circuit further comprises a first hardmask disposed over the first conductive material of said first set of wires.

A method of depositing wires, comprising:

• forming a plurality of first trenches in a surface of a dielectric layer;
• forming a plurality of first wires, wherein each of said first wires are formed in each of said first trenches and said first wires are formed of a first material having a first bulk resistivity;
• forming a plurality of second trenches in said surface of said dielectric layer;
• and
• forming a plurality of second wires, wherein each of said second wires are formed in each of said second trenches and said second wires are formed of a second material having a second bulk resistivity;
• wherein:
• said first bulk resistivity and second bulk resistivity are different;
• and
• the plurality of first trenches and the plurality of second trenches are formed by spacer based pitch division.

An integrated circuit, comprising:

• a first dielectric layer including a surface;
• a plurality of first trenches defined in said dielectric layer surface;
• a plurality of first wires, wherein each of said first wires are formed in each of said first trenches, wherein said first wires comprise a first material having a first bulk resistivity;
• a plurality of second trenches defined in said dielectric layer surface;
• and
• a plurality of second wires;
• wherein:
• each of said second wires are formed in each of said second trenches;
• said second wires comprise a second material having a second bulk resistivity;
• said first bulk resistivity and said second bulk resistivity are different;
• and
• said first wires exhibit a first height and said second wires exhibit a second height that is different from said second height.