Intelligent chip placement within a three-dimensional chip stack

An integrated circuit (IC) stack device comprising:

• a supplementary IC having
• a first side,
• a first set of cores with first enabled cores and first disabled cores, the first set of cores on the first side,
• a second side opposing the first side, and
• a first data bus;
• a primary IC interfaced with the supplementary IC and having
• a second set of cores with second enabled cores and second disabled cores,
• wherein the second disabled cores include at least one functional disabled core and at least one non-functional disabled core,
• wherein the first enabled cores include at least one functional enabled core corresponding to the at least one non-functional disabled core on the primary IC and at least one functional spare core corresponding to the at least one functional disabled core on the primary IC, the at least one functional spare core selected to balance thermal distribution of enabled cores within the IC stack,
• a third side on which the second set of cores is located,
• a fourth side opposing the third side, and
• a second data bus configured to facilitate communication between the first set of cores and the second set of cores;
• a power source configured to deliver power to the primary IC via one or more through-silicon vias (TSVs) in the supplementary IC, wherein the supplementary IC is located between the primary IC and the power source;
• and
• a cooling element located such that the primary IC is between the cooling element and the supplementary IC, the primary IC having a higher number of functional cores than the supplementary IC and the cooling element adapted to facilitate heat dissipation of the first and second enabled cores of the supplementary IC and the primary IC.