Chip package-in-package and method thereof
AssigneeIntel Deutschland GmbH
InventorsThorsten Meyer, Sven Albers, Andreas Wolter
Life of this patent
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Abstract
An electronic package includes an interposer, a die attached to a first side of the interposer, an embedded electronic package attached to a second side of the interposer, an encapsulation compound, a set of vias providing electrical paths from a first side of the electronic package to the interposer through the encapsulation compound, and a redistribution layer electrically redistributing the set of vias to form a set of interconnect-pads. Either the die or the embedded electronic package, or both, are electrically connected to the interposer.
Claims11
A chip package, comprising:
- a first substrate;
- a first chip arranged over the first substrate;
- a second substrate arranged over the first chip on a top side of the first chip facing away from the first substrate, wherein the second substrate comprises one or more contacts and at least one electrically conductive line coupled to at least one of the one or more contacts, wherein the second substrate includes an overhanging lateral dimension section extending beyond a lateral dimension of the first chip;
- and
- a first encapsulation material at least partially embedding a second chip;
- a second encapsulation material at least partially encapsulating the first encapsulation material, the second chip, the second substrate and the first chip;
- one or more contact holes, each substantially vertically extending through the encapsulation material to electrically couple to at least one of the one or more contacts of the second substrate in the overhanging lateral dimension section of the second substrate;
- and
- wherein the second chip is arranged over and electrically connected to the second substrate at a non-overhanging lateral dimension so as to be in electrical connection with at least one of the one or more contact holes
- wherein a surface of the first chip facing the second chip is attached to and is electrically connected to a surface of the second substrate facing away from the second chip.
A chip package, comprising:
- a first chip arranged over a substrate;
- an interposer arranged over the first chip;
- an embedded package arranged over the interposer, the embedded package comprising a second chip at least partially encapsulated by an encapsulation material, the second chip electrically coupled to the interposer;
- a second encapsulation material encapsulation at least partially encapsulating the embedded package, the interposer and the first chip;
- and
- a plurality of vias, each via extending, substantially vertically, from a side of the interposer facing toward the first chip through the second encapsulation material to a redistribution layer disposed on a bottom side of the substrate facing away from the first chip;
- and
- a plurality of second vias, each of the second vias extending, substantially vertically, from a side of the interposer facing toward the second chip through the second encapsulation material to a top surface of the second encapsulation material.
Dependencies are inferred from the claim text.