Block patterning process for post fin

A method of forming a semiconductor structure comprising:

• forming a plurality of semiconductor fins on a substrate comprising a buried insulator layer over a handle substrate;
• forming a gate structure over a portion of each of the plurality of semiconductor fins;
• forming a contact trench in the substrate, wherein the contact trench extends through the buried insulator layer and into the handle substrate;
• forming an organic planarization layer (OPL) over the substrate, wherein the OPL is deposited to a minimum thickness sufficient to fill in spaces between the plurality of semiconductor fins and to cover the plurality of semiconductor fins, and the OPL fills in the contact trench, and wherein a top surface of the OPL is non-planar;
• forming a developable antireflective coating (DARC) layer on the top surface of the OPL, wherein the DARC layer provides a substantially planar top surface;
• forming a photoresist layer on the top surface of the DARC layer;
• exposing a portion of the photoresist layer to a radiation, the radiation creating a pattern in exposed portion of the photoresist layer and a portion of the DARC layer underlying the exposed portion of the photoresist layer;
• removing the exposed portion of the photoresist layer and the portion of the DARC layer underlying the exposed portion of the photoresist layer to expose a portion of the OPL;
• and
• removing exposed portion of the OPL to form an opening, wherein the opening exposes a first set of the plurality of semiconductor fins and leaves a second set of the plurality of semiconductor fins covered.