Semiconductor device and method of manufacturing the same
AssigneeThe Institute of Microelectronics Chinese Academy of Science
InventorsHuaxiang Yin, Xiaolong Ma, Qiuxia Xu, Dapeng Chen
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Abstract
The present invention discloses a semiconductor device, comprising a first MOSFET; a second MOSFET; a first stress liner covering the first MOSFET and having a first stress; a second stress liner covering the second MOSFET and having a second stress; wherein the second stress liner and/or the first stress liner comprise(s) a metal oxide. In accordance with the high-stress CMOS and method of manufacturing the same of the present invention, a stress layer comprising a metal oxide is formed selectively on PMOS and NMOS respectively by using a CMOS compatible process, whereby carrier mobility of the channel region is effectively enhanced and the performance of the device is improved.
Claims9
A method of manufacturing a semiconductor device, comprising the following steps:
- forming a first MOSFET and a second MOSFET;
- forming a second stress liner having a second stress on the second MOSFET selectively;
- forming a first stress liner having a first stress on the first MOSFET selectively;
- and
- forming a buffer layer below the first stress liner and/or the second stress liner to reduce interface defects and adjust the first and/or second stress;
- and
- completing following processes,
- wherein the second stress liner and/or the first stress liner include(s) a stack of metal oxides, including at least one of a refractory metal oxide and diamond-like amorphous carbon (DLC), and wherein the second stress liner and the first stress liner does not overlap, and
- wherein the refractory metal oxide includes an iron based oxide.
A method of manufacturing a semiconductor device, comprising the following steps:
- forming a first MOSFET and a second MOSFET;
- forming a second stress liner having a second stress on the second MOSFET selectively;
- forming a first stress liner having a first stress on the first MOSFET selectively;
- and
- forming a buffer layer below the first stress liner and/or the second stress liner to reduce interface defects and adjust the first and/or second stress;
- and
- completing following processes,
- wherein the second stress liner and/or the first stress liner include(s) a stack of amorphous oxide semiconductors and diamond-like amorphous carbon (DLC), and wherein the second stress liner and the first stress liner does not overlap, and
- wherein the amorphous oxide semiconductor comprises an In-doped ZnO based semiconductor or other binary or multi-element amorphous oxide semiconductor;
- the In-doped ZnO based semiconductor comprises at least one of InGaZnO, InZnO, HfInZnO, TaInZnO, ZrInZnO, YInZnO, AlInZnO and SnInZnO, and the other binary or multi-element amorphous oxide semiconductor comprises at least one of In2O3, ZTO, ITO, ZnO and SnOx.
Dependencies are inferred from the claim text.