Semiconductor devices and methods of manufacturing the same

A method of manufacturing a semiconductor device, the method comprising:

• forming a pair of first gate structures on a cell region of a substrate, the substrate including the cell region in which memory cells are formed and a logic region in which logic elements are formed, the logic region having a high voltage region, an ultra high voltage region and a low voltage region, and each of the first gate structures including a first gate insulation layer pattern, a floating gate, a dielectric layer pattern, a control gate and a hard mask;
• forming a spacer layer on the pair of first gate structures and the substrate;
• etching the spacer layer to form a spacer and a second gate insulation layer pattern, the spacer being formed on a sidewall of each of the first gate structures, and the second gate insulation layer pattern being formed on the ultra high voltage region of the substrate;
• forming a tunnel insulation layer on the pair of first gate structures, the spacer, the second gate insulation layer pattern and the substrate;
• etching the tunnel insulation layer to form a tunnel insulation layer pattern and a third gate insulation layer pattern, the tunnel insulation layer pattern being formed on an inner sidewall of each of the first gate structures and a portion of the substrate between the pair of first gate structures, and the third gate insulation layer pattern being formed on the high voltage region of the substrate and on the second gate insulation layer pattern;
• forming a word line on an outer sidewall of each of the first gate structures;
• and
• forming a gate electrode on the third gate insulation layer pattern and on the low voltage region of the substrate.

A method of manufacturing a semiconductor device, the method comprising:

• forming a split gate structure on a cell region of a substrate including the cell region and a logic region, the split gate structure including a first gate insulation layer pattern, a floating gate, and a control gate that are stacked sequentially;
• concurrently forming a spacer and a second gate insulation layer pattern, the spacer being formed on a sidewall of the split gate structure, and the second gate insulation layer pattern being formed on an ultra high voltage portion of the logic region;
• and
• forming a gate electrode on a high voltage portion of the logic region, the second gate insulation layer pattern, and a low voltage portion of the logic region.