Forming gate and source/drain contact openings by performing a common etch patterning process

A method of forming conductive structures for a transistor device formed above an active region of a semiconducting substrate surrounded by an isolation region, the method comprising:

• forming a gate structure above said active region and said isolation region;
• forming a gate cap layer above said gate structure;
• forming at least one layer of material above said active region;
• forming an opening in said at least one layer of material, said opening exposing source/drain regions of said transistor and a first portion of said gate cap layer positioned above said active region;
• forming a conductive material above said exposed source/drain regions and above said first portion of said gate cap layer;
• performing a first recess etching process on a second portion of said gate cap layer positioned above said isolation region so as to thereby define a reduced-thickness second portion of said gate cap layer positioned above said isolation region;
• performing at least one second recess etching process to recess said conductive material so as to define separate initial source/drain contacts positioned on opposite sides of said gate structure;
• forming an insulating material above said source/drain contacts and above said reduced-thickness second portion of said gate cap layer;
• performing a common etching process sequence through a patterned masking layer to define a gate contact opening that extends through said reduced-thickness second portion of the gate cap layer and to define a plurality of separate source/drain contact openings in said layer of insulating material, each of which are positioned above one of said initial source/drain contacts;
• forming a conductive gate contact structure in said gate contact opening such that said conductive gate contact structure is conductively coupled to said gate structure;
• and
• forming a conductive source/drain contact structure in each of said source/drain contact openings such that said conductive source/drain contact structure is conductively coupled to an underlying initial source/drain contact.

A method, comprising:

• forming an isolation region in a semiconducting substrate, said isolation region surrounding and defining an active region in said semiconducting substrate;
• forming a gate structure above said semiconducting substrate, a first portion of said gate structure extending across said active region and a second portion of said gate structure extending across said isolation region;
• forming an initial gate cap layer above said gate structure, said initial gate cap layer comprising a plurality of material layers;
• masking a first gate cap portion of said initial gate cap layer formed above said first portion of said gate structure and exposing a second gate cap portion of said initial gate cap layer formed above said second portion of said gate structure;
• performing at least one etching process on said exposed second gate cap portion to remove at least one of said plurality of material layers comprising said initial gate cap layer selectively to at least one underlying layer of said plurality of material layers so as to form a modified gate cap layer comprising said first gate cap portion and a modified second gate cap portion having a reduced-thickness portion relative to said first gate cap portion;
• forming a layer of insulating material above said modified gate cap layer;
• forming a gate contact opening extending through said layer of insulating material and through said reduced-thickness portion of said modified second gate cap portion of said modified gate cap layer, said gate contact opening exposing said second portion of said gate structure;
• and
• forming a gate contact in said gate contact opening.