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US 9,312,156 B2Granted
Thin film transistor
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorHidekazu Miyairi
Life of this patent
Estimating the term…
Abstract
A thin film transistor includes a gate electrode; a gate insulating layer which is provided to cover the gate electrode; a semiconductor layer which is provided over the gate insulating layer to overlap with the gate electrode; an impurity semiconductor layer which is partly provided over the semiconductor layer and which forms a source region and a drain region; and a wiring layer which is provided over the impurity semiconductor layer, where a width of the source region and the drain region is narrower than a width of the semiconductor layer, and where the width of the semiconductor layer is increased at least in a portion between the source region and the drain region.
Claims20
A semiconductor device comprising:
- a first wiring layer;
- a gate insulating layer covering the first wiring layer;
- a semiconductor layer over the gate insulating layer, overlapping the first wiring layer, and comprising a channel formation region;
- first and second impurity semiconductor layers on the semiconductor layer, the first and second impurity semiconductor layers being configured to be a source region and a drain region;
- and
- second wiring layers over the first and second impurity semiconductor layers;
- wherein the semiconductor layer includes a pair of first regions each having a first width along a channel formation region width direction and a second region provided between the pair of first regions and having a second width along the channel formation region width direction, the second width being larger than the first width,
- wherein the second wiring layers overlap with at least a portion of the second region, and
- wherein each of edges of the first and second impurity semiconductor layers is in direct contact with the semiconductor layer on the first wiring layer.
6 more elements
A semiconductor device comprising:
- a first wiring layer;
- a gate insulating layer covering the first wiring layer;
- a semiconductor layer over the gate insulating layer, overlapping the first wiring layer, and comprising a channel formation region;
- first and second impurity semiconductor layers on the semiconductor layer, the first and second impurity semiconductor layers being configured to be a source region and a drain region;
- and
- second wiring layers over the first and second impurity semiconductor layers;
- wherein the semiconductor layer includes a pair of first regions each having a first width along a channel formation region width direction and a second region provided between the pair of first regions and having a second width along the channel formation region width direction, the second width being larger than the first width,
- wherein the second wiring layers overlap with at least a portion of the second region,
- wherein each of edges of the first and second impurity semiconductor layers is in direct contact with the semiconductor layer on the first wiring layer, and
- wherein a distance between the source region and the drain region is shorter than a length of the second region.
7 more elements
A display device comprising:
- a first wiring layer;
- a gate insulating layer covering the first wiring layer;
- a semiconductor layer over the gate insulating layer, overlapping the first wiring layer, and comprising a channel formation region;
- first and second impurity semiconductor layers on the semiconductor layer, the first and second impurity semiconductor layers being configured to be a source region and a drain region;
- second wiring layers over the first and second impurity semiconductor layers;
- a pixel electrode layer connected to one of the second wiring layers,
- wherein the semiconductor layer includes a pair of first regions each having a first width along a channel formation region width direction and a second region provided between the pair of first regions and having a second width along the channel formation region width direction, the second width being larger than the first width,
- wherein the second wiring layers overlap with at least a portion of the second region, and
- wherein each of edges of the first and second impurity semiconductor layers is in direct contact with the semiconductor layer on the first wiring layer.
6 more elements
A display device comprising:
- a first wiring layer;
- a gate insulating layer covering the first wiring layer;
- a semiconductor layer over the gate insulating layer, overlapping the first wiring layer, and comprising a channel formation region;
- first and second impurity semiconductor layers on the semiconductor layer, the first and second impurity semiconductor layers being configured to be a source region and a drain region;
- second wiring layers over the first and second impurity semiconductor layers;
- and
- a pixel electrode layer connected to one of the second wiring layers,
- wherein the semiconductor layer includes a pair of first regions each having a first width along a channel formation region width direction and a second region provided between the pair of first regions and having a second width along the channel formation region width direction, the second width being larger than the first width,
- wherein the second wiring layers overlap with at least a portion of the second region, wherein a distance between the source region and the drain region is shorter than a length of the second region, and
- wherein each of edges of the first and second impurity semiconductor layers is in direct contact with the semiconductor layer on the first wiring layer.
7 more elements
Dependencies are inferred from the claim text.