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US 9,312,140 B2Granted
Semiconductor structures having low resistance paths throughout a wafer
AssigneeInternational Business Machines Corporation
InventorsJeffrey P. Gambino, Thomas J. Hartswick, Zhong-Xiang He, Anthony K. Stamper, Eric J. White
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Abstract
A semiconductor structure with low resistance conduction paths and methods of manufacture are disclosed. The method includes forming at least one low resistance conduction path on a wafer, and forming an electroplated seed layer in direct contact with the low resistance conduction path.
Claims12
A method, comprising:
- forming at least one low resistance conduction path into an interlevel dielectric material and an underlying substrate of a wafer, within dicing channels of the wafer;
- forming a barrier layer in direct contact with the low resistance conductive path;
- and
- forming an electroplated seed layer in direct contact with the barrier layer.
1 more element
A method, comprising:
- forming at least two metal filled vias within an insulator layer and a substrate of a wafer, and within a dicing channel of the wafer;
- and
- forming a barrier layer on a patterned upper insulator layer, in direct contact with the least two metal filled vias;
- forming an electroplated seed layer in direct contact with the barrier layer,
- wherein the forming of the electroplated seed layer comprises:
- forming the upper insulator layer on the insulator layer;
- patterning the upper insulator layer to form an opening which exposes the at least two metal filled vias;
- and
- forming the electroplated seed layer on a surface of the upper insulator layer including within the opening.
6 more elements
A method, comprising:
- forming at least two metal filled vias into an insulating layer and an underlying substrate of a wafer, wherein the at least two metal filled vias are formed within dicing channels of the wafer;
- forming an upper insulator layer on the insulating layer;
- patterning the upper insulator layer to form an opening which exposes the at least two metal filled vias;
- and
- forming an electroplated seed layer in the opening in electrical contact with the at least two metal filled vias.
2 more elements
Dependencies are inferred from the claim text.