Wafer structure for electronic integrated circuit manufacturing

A method of forming a wafer structure comprising:

• forming a first region from a device wafer having at least one major surface, a thickness, and a conductivity profile of a first conductivity type substantially parallel to said at least one major surface;
• forming a second region from a separate handle wafer having a thickness, and a second conductivity profile of the first conductivity type of said first region, such second conductivity profile being substantially different than the conductivity profile of said first region, such that said second region is in electrical contact with said first region opposite the major surface of said first region;
• forming a bond interface region between said first region and said second region;
• and
• placing impurity sites in said first region, such impurity sites being substantially electrically inactive over a temperature range,
• wherein the conductivity profile of said first region transitions abruptly to the conductivity profile of said second region within the interface region,
• wherein said first region, said second region, and said interface region comprise the same semiconductor material, and
• wherein said impurity sites are selected from the group of isotopes consisting of silicon, carbon, fluorine, sulfur, chlorine, nitrogen, or defects selected from the group consisting of lattice vacancies, interstitial defects, Frenkel defect pairs, crystal dislocations, or a combination of said isotopes and defects.