Compound semiconductor integrated circuit and method to fabricate same

A structure comprising:

• a compound semiconductor substrate comprising a compound semiconductor material comprising a Group III-V compound semiconductor material having a first large bandgap energy, the first large bandgap energy being greater than about 1 eV, the compound semiconductor substrate having a top surface, and the top surface having a first portion and a second portion positioned laterally adjacent to and level with the first portion;
• a first compound semiconductor layer immediately adjacent to the first portion of the top surface of the compound semiconductor substrate, the first compound semiconductor layer being comprised of a first additional compound semiconductor material that is different from the compound semiconductor material and that has a second large bandgap energy, the second large bandgap energy being that is greater than about 0.75 eV;
• a second compound semiconductor layer immediately adjacent to the second portion of the top surface of the compound semiconductor substrate, the second compound semiconductor layer being physically separated from the first compound semiconductor layer and comprising a second additional compound semiconductor material having a small bandgap energy, the small bandgap energy being equal to or less than about 0.75 eV;
• and
• a first transistor and a second transistor,
• the first transistor having a first channel positioned laterally between first source and drain regions and a first gate on the first channel, the first channel and the first source and drain regions being entirely within the first compound semiconductor layer immediately adjacent to the first portion of the top surface and the first gate being immediately adjacent to the first compound semiconductor layer, and
• the second transistor having a second channel positioned laterally between second source and drain regions and a second gate on the second channel, the second channel and the second source and drain regions being entirely within the second compound semiconductor layer immediately adjacent to the second portion of the top surface and the second gate being immediately adjacent to the second compound semiconductor layer.