Semiconductor memory apparatus and data processing system with main memory blocks and redundant memory blocks sharing a common global data line
AssigneeSK hynix Inc.
InventorMin Su Kim
Life of this patent
Estimating the term…
Abstract
A semiconductor memory apparatus includes: a memory area including a plurality of memory banks having main memory areas configured to transmit and receive data to and from the outside through a plurality of global data lines, respectively, and one or more redundancy memory areas configured to use any one of the global data lines as a common global data line; and a controller configured to control data to be transmitted and received through the common global data line, as a redundancy program mode, a redundancy read mode, or a redundancy erase mode is enabled.
Claims14
A semiconductor memory apparatus comprising:
- a main memory area comprising a plurality of banks;
- one or more redundancy memory areas;
- a plurality of global data lines configured to exchange data of respective banks with the outside;
- a main page buffer coupled to the main memory area;
- redundancy page buffers coupled to respective redundancy memory areas;
- and
- a controller configured to control a redundancy program mode in which, as a program command, an access address, and data are provided, the data is inputted to the main page buffer, and the data of the main page buffer is transferred to a corresponding redundancy page buffer when the main memory area is repaired,
- wherein one or more of the global data lines comprise a common global data line which is commonly shared by the redundancy memory areas and the main memory area;
- and
- wherein the controller sets the main page buffer in a program-inhibited state, after the data of the main page buffer is transferred to the corresponding redundancy page buffer.
A data processing system comprising:
- a host apparatus;
- and
- a semiconductor memory apparatus coupled to the host apparatus through a host interface,
- wherein the semiconductor memory apparatus comprises a main memory area comprising a plurality of banks and one or more redundancy memory areas;
- the one or more redundancy memory areas configured to share a common global data line with the main memory area;
- a main storage unit coupled to the main memory area;
- one or more redundancy storage units coupled to respective redundancy memory areas;
- and
- a controller comprising an address generator configured to generate an internal column address according to whether a column address is repaired or not, and a storage unit selector configured to generate a column select signal in response to the internal column address and a storage unit select signal,
- wherein the address generator outputs the internal column address in response to a control clock signal, the internal column address is outputted as a redundancy program mode, a redundancy read mode, or a redundancy erase mode is enabled.
Dependencies are inferred from the claim text.