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US 9,312,031 B2Granted
Semiconductor device and test method thereof
AssigneePS4 Luxco S.a.r.l.
InventorNaohisa Nishioka
Life of this patent
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Abstract
A semiconductor chip includes a memory array including a plurality of memory cells, a plurality of terminals including a plurality of test terminals to output a result of a specific test, and a circuit that outputs the result to a selected one of the plurality of test terminals based on a chip identification data.
Claims20
A semiconductor device comprising:
- a memory cell array;
- a first through silicon via for receiving a test clock signal;
- a second through silicon via for receiving a test enable signal;
- a third through silicon via;
- and
- a test circuit configured to receive the test clock signal, perform a test of the memory cell array after receiving the test enable signal, and provide a test result signal to the third through silicon via.
3 more elements
A semiconductor device comprising:
- a plurality of core chips each having:
- a memory cell array;
- a first through silicon via, commonly connected to the first through silicon via of each of the plurality of core chips, for receiving a test clock signal;
- a second through silicon via, commonly connected to the second through silicon via of each of the plurality of core chips, for receiving a test enable signal;
- a third through silicon via;
- and
- a test circuit configured to receive the test clock signal, perform a test of the memory cell array after receiving the test enable signal, and provide a test result signal to the third through silicon via.
4 more elements
Dependencies are inferred from the claim text.