Memory device and associated controlling method
AssigneeMacronix International Co., Ltd.
InventorsWin-San Khwa, Chao-I Wu, Tzu-Hsiang Su
Life of this patent
Estimating the term…
Abstract
A memory device and associated controlling method are provided. The memory device includes a memory cell array, a sensing unit and a controller. The memory cell array has a plurality of memory cells. The sensing unit is electrically connected to the memory cell array and the controller. The sensing unit senses characteristic of a memory cell of the plurality of memory cells. The controller determines whether the characteristic of the one of the memory cells deviates and accordingly controls the memory cell array.
Claims20
A memory device, comprising:
- a memory cell array having a plurality of memory cells;
- a sensing unit, electrically connected to the memory cell array, for sensing a characteristic of a memory cell among the plurality of memory cells;
- a controller, electrically connected to the sensing unit, for determining whether the characteristic of the memory cell deviates and accordingly controlling the memory cell array;
- and
- a pulse generator, electrically connected to the memory cell array, for applying at least one testing pulse to the memory cell before the sensing unit senses the characteristic of the memory cell, wherein
- when the at least one testing pulse is applied to the memory cell during a reset operation, a duration of the at least one testing pulse is shorter than that of a reset pulse, and an amplitude of the at least one testing pulse is smaller than that of the reset pulse.
A controlling method applied to a memory cell array comprising a plurality of memory cells, the controlling method comprising steps of:
- applying at least one testing pulse to a memory cell among the plurality of memory cells, wherein when the at least one testing pulse is applied to the memory cell during a reset operation, a duration of the at least one testing pulse is shorter than that of a reset pulse, and an amplitude of the at least one testing pulse is smaller than that of the reset pulse;
- sensing a characteristic of the memory cell;
- determining whether the characteristic of the memory cell deviates;
- and
- controlling the memory cell array in response to whether the characteristic of the memory cell deviates.
A memory device, comprising:
- a memory cell array having a plurality of memory cells;
- a sensing unit, electrically connected to the memory cell array, for sensing a characteristic of a memory cell among the plurality of memory cells;
- a controller, electrically connected to the sensing unit, for determining whether the characteristic of the memory cell deviates and accordingly controlling the memory cell array;
- and
- a pulse generator, electrically connected to the memory cell array, for applying at least one testing pulse to the memory cell before the sensing unit senses the characteristic of the memory cell, wherein when the at least one testing pulse is applied to the memory cell during a set operation, a duration of the at least one testing pulse is shorter than that of a set pulse, and an amplitude of the at least one testing pulse is smaller than that of the set pulse.
A controlling method applied to a memory cell array comprising a plurality of memory cells, the controlling method comprising steps of:
- applying at least one testing pulse to a memory cell among the plurality of memory cells, wherein when the at least one testing pulse is applied to the memory cell during a set operation, a duration of the at least one testing pulse is shorter than that of a set pulse, and an amplitude of the at least one testing pulse is smaller than that of the set pulse;
- sensing a characteristic of the memory cell;
- determining whether the characteristic of the memory cell deviates;
- and
- controlling the memory cell array in response to whether the characteristic of the memory cell deviates.
Dependencies are inferred from the claim text.