Method for detecting permanent faults of an address decoder of an electronic memory device

A memory, comprising:

• an array of memory locations;
• an address decoder having addressing portions;
• an error detecting module configured to detect an error at a first one of the memory locations having an address that corresponds to a group of the addressing portions;
• and
• a test module, including:
• a first submodule configured to write first test data to the first one of the memory locations in response to detection of the error;
• a second submodule configured to write second test data to second ones of the memory locations having respective addresses that each correspond to a subgroup of the group of addressing portions in response to detection of the error, the second test data different than the first test data;
• a third submodule configured to read data from the first one of the memory locations after writing of the second test data by the second submodule;
• and
• a fourth submodule configured to compare the data read by the third submodule to the first test data and indicate that a fault exists in the address decoder if the data read by the third submodule and first test data are not equal.

An electronic system, comprising:

• a memory, comprising:
• an array of memory locations;
• an address decoder having addressing portions;
• an error detecting module configured to detect an error at a first one of the memory locations having an address that corresponds to a group of the addressing portions;
• and
• a test module, including
• a first submodule configured to write first test data to the first one of the memory locations in response to detection of the error,
• a second submodule configured to write second test data to second ones of the memory locations having respective addresses that each correspond to a subgroup of the group of addressing portions in response to detection of the error, the second test data different than the first test data,
• a third submodule configured to read data from the first one of the memory locations after writing of the second test data by the second submodule, and
• a fourth submodule configured to compare the data read by the third submodule to the first test data and indicate that a fault exists in the address decoder if the data read by the third submodule and first test data are not equal;
• and
• an integrated circuit coupled to the memory.

A method, comprising:

• detecting an error at a first memory location using an error detecting module;
• addressing the first memory location via selection circuitry in response to detection of the error;
• writing first test data to the first memory location in response to detection of the error;
• addressing each of second memory locations via a respective portion of the selection circuitry in response to detection of the error;
• writing second test data to the second memory locations in response to detection of the error, the second test data different than the first test data;
• reading data from the first memory location after writing of the second test data;
• and
• comparing the read data to the first test data and indicate that a fault exists in the selection circuitry if the read data and first test data are not equal.

A method of determining whether a fault exists within an address decoder for a memory, the method comprising:

• writing a test word to a memory location of the memory associated with a portion of the address decoder by addressing the memory location using the address decoder;
• reading a comparison word from the memory location by addressing the memory location using the address decoder;
• detecting an undiagnosed error if the test word and comparison word are not equal;
• and
• based on detection of the undiagnosed error,
• writing a new test word to the memory location by addressing the memory location using the address decoder,
• reading a new comparison word from the memory location by addressing the memory location using the address decoder,
• detecting a potential fault within the address decoder if the new test word and new comparison word are not equal, and
• based on detection of the potential fault within the address decoder,
• writing a further test word to a new memory location of the memory associated with a subset of the portion of the address decoder by addressing the new memory location using the address decoder,
• reading a further comparison word from the new memory location by addressing the new memory location using the address decoder, and
• detecting a fault within the address decoder if the further test word and further comparison word are not equal.