Zoned erase verify in three dimensional nonvolatile memory
AssigneeSanDisk Technologies LLC
InventorsMrinal Kochar, Gautam Dusija, Chris Avila, Yingda Dong, Man Mui, Yichao Huang, Deepak Raghu
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Abstract
In a three-dimensional nonvolatile memory, when a block erase failure occurs, zones within a block may be separately verified to see if some zones pass verification. Zones that pass may be designated as good zones and may subsequently be used to store user data while bad zones in the same block may be designated as bad and may not be used for subsequent storage of user data.
Claims22
A method of operating blocks of memory cells in a block-erasable NAND flash memory comprising:
- performing a block erase operation that applies an erase voltage to all word lines of the block;
- subsequently performing a block erase verify operation to determine if the block erase operation was successful;
- in response to determining that the block erase operation was not successful performing a sub-block erase verify operation that applies an erase verify voltage to a first subset of word lines of the block and does not apply the erase verify voltage to a second subset of word lines of the block to determine if the block erase operation successfully erased the first subset of word lines;
- and
- if the sub-block erase verify operation indicates that the first subset of word lines is erased then designating the first subset of word lines as a good subset for subsequent storage of data.
A method of operating a block of memory cells in a monolithic three-dimensional block-erasable memory device that has a plurality of device levels vertically disposed above a silicon substrate comprising:
- performing a block erase operation that applies an erase voltage to word lines in all of the plurality of memory device levels of the block;
- subsequently performing a block erase verify operation to determine if the block erase operation was successful;
- in response to determining that the block erase operation was not successful performing a series of sub-block erase testing operations that apply an erase verify voltage to word lines of a selected sub-block of the block while not applying the erase verify voltage to word lines of unselected sub-blocks of the block to verify if word lines of the selected sub-block are erased;
- subsequently mapping each of the sub-blocks as either a good sub-block or a bad sub-block according to the results of the sub-block testing operations;
- and
- subsequently storing user data in good sub-blocks while prohibiting storage of user data in bad sub-blocks.
A monolithic block-erasable three-dimensional semiconductor memory device formed in multiple physical levels of memory elements disposed above a silicon substrate comprising:
- a first plurality of blocks that pass block erase testing and are designated for block erase in which an erase voltage is applied to word lines of all physical levels of the block at the same time;
- and
- a second plurality of blocks that fail block erase testing and subsequently pass sub-block erase testing and are configured for sub-block operation in which at least one sub-block that includes a plurality of word lines is designated as a bad sub-block and is not used to store user data while at least one other sub-block that includes a plurality of word lines is designated as a good sub-block and is used to store user data.
Dependencies are inferred from the claim text.