Flash memory device having efficient refresh operation

Abstract

Provided is a flash memory device capable of efficiently performing a refresh operation. The flash memory device includes a normal memory array including a plurality of normal memory cells arranged in a matrix of word lines and bit lines, wherein the plurality of normal memory cells are divided into a plurality of memory blocks and are programmable and erasable; a refresh address generation unit configured to generate a refresh block address, wherein the refresh block address is sequentially increased in response to activation of a refresh driving signal; and a refresh driving unit driven to refresh a memory block specified by the refresh block address among the memory blocks of the normal memory array in a unit refresh frame, and generate the refresh driving signal. In the flash memory device, a refresh operation may be efficiently performed to fix a data disturbance.

Dependencies are inferred from the claim text.