Methods for reducing body effect and increasing junction breakdown voltage

A non-volatile storage system, comprising:

• a semiconductor memory array, the semiconductor memory array includes a plurality of word lines;
• a word line switch transistor connected to a first word line of the plurality of word lines, the word line switch transistor includes a polysilicon gate;
• a first poly shield, the first poly shield is located next to the polysilicon gate of the word line switch transistor such that there is no intervening polysilicon structure between the polysilicon gate and the first poly shield;
• a shield biasing control circuit in communication with the first poly shield, the shield biasing control circuit configured to identify a memory operation to be performed on the semiconductor memory array, the shield biasing control circuit configured to determine a first voltage to be applied to the first poly shield based on the memory operation, the shield biasing control circuit configured to set the first poly shield to the first voltage during the memory operation;
• and
• one or more managing circuits in communication with the semiconductor memory array, the one or more managing circuits configured to cause the word line switch transistor to transfer a word line voltage to the first word line during the memory operation and subsequent to the first poly shield being set to the first voltage.

A method for operating a non-volatile storage system, comprising:

• acquiring a memory command associated with performing a memory operation on a memory array, the memory array includes a plurality of word lines;
• determining a first voltage to be applied to a first poly shield based on the memory operation, the first poly shield is located next to a polysilicon gate of a word line switch transistor such that there is no intervening polysilicon structure between the polysilicon gate and the first poly shield, the determining a first voltage includes determining the first voltage based on a lowest voltage to be applied to any of the plurality of word lines during the memory operation;
• biasing the first poly shield to the first voltage;
• and
• performing the memory operation, the performing the memory operation includes transferring a word line voltage to a first word line of the plurality of word lines using the word line switch transistor, the transferring a word line voltage to the first word line is performed subsequent to the biasing the first poly shield to the first voltage, the biasing the first poly shield to the first voltage causes a reduction in a threshold voltage of the word line switch transistor during the memory operation.