Programming of drain side word line to reduce program disturb and charge loss

A method for programming a memory device, comprising:

• in response to a command to program data in a set of memory cells in a set of NAND strings, where the memory cells are connected to a plurality of word lines extending between a drain-side word line at a drain-end of the set of NAND strings and a source-side word line at a source-side of the set of NAND strings, programming memory cells connected to the drain-side word line to a plurality of target data states using a first set of verify voltages, wherein the memory cells connected to the drain-side word line are programmed before programming memory cells connected to other word lines of the plurality of word lines, and each memory cell of the set of memory cells comprises a charge-trapping material;
• and
• subsequently programming memory cells connected to another word line of the plurality of word lines to the plurality of target data states using a second set of verify voltages, wherein a lowest verify voltage of the first set of verify voltages is higher than a lowest verify voltage of the second set of verify voltages.