Accessing memory cells in parallel in a cross-point array
AssigneeMicron Technology, Inc.
InventorHernan A. Castro
Life of this patent
Estimating the term…
Abstract
Methods and structures for accessing memory cells in parallel in a cross-point array include accessing in parallel a first memory cell disposed between a first selected column and a first selected row and a second memory cell disposed between a second selected column different from the first selected column and a second selected row different from the first selected row. Accessing in parallel includes simultaneously applying access biases between the first selected column and the first selected row and between the second selected column and the second selected row. The accessing in parallel is conducted while the cells are in a thresholded condition or while the cells are in a post-threshold recovery period.
Claims37
A method of accessing memory cells in parallel in a cross-point array comprising:
- accessing in parallel a first memory cell, disposed between a first selected column and a first selected row, and a second memory cell, disposed between a second selected column different from the first selected column and a second selected row different from the first selected row, wherein accessing in parallel includes writing, erasing or reading by simultaneously applying a first access bias between the first selected column and the first selected row and applying a second access bias between the second selected column and the second selected row.
A method of accessing memory cells in parallel in a cross-point array comprising:
- accessing in parallel a first memory cell, disposed between a first selected column and a first selected row, and a second memory cell, disposed between a second selected column different from the first selected column and a second selected row different from the first selected row, wherein accessing in parallel includes simultaneously applying a first access bias between the first selected column and the first selected row and applying a second access bias between the second selected column and the second selected row;
- prior to accessing the first memory cell, thresholding the first memory cell by applying a first threshold bias between the first selected column and the first selected row;
- and
- prior to accessing the second memory cell, thresholding the second memory cell by applying a second threshold bias between the second selected column and the second selected row.
A memory device configured to access memory cells in parallel in a cross-point array comprising:
- a memory controller configured to write, erase or read in parallel a first memory cell, the first memory cell disposed between a first selected column and a first selected row, and a second memory cell, the second memory cell disposed between a second selected column different from the first selected column and a second selected row different from the first selected row, wherein the memory controller is configured to simultaneously apply a first access bias between the first selected column and the first selected row and to apply a second access bias between the second selected column and the second selected row.
A memory device configured to access memory cells in parallel in a cross-point array comprising:
- a memory controller configured to access in parallel a first memory cell, the first memory cell disposed between a first selected column and a first selected row, and a second memory cell, the second memory cell disposed between a second selected column different from the first selected column and a second selected row different from the first selected row, wherein the memory controller is configured to simultaneously apply a first access bias between the first selected column and the first selected row and apply a second access bias between the second selected column and the second selected row, wherein the memory controller is configured to:
- prior to accessing the first memory cell, threshold the first memory cell by applying a first threshold bias between the first selected column and the first selected row, and
- prior to accessing the second memory cell, threshold the second memory cell by applying a second threshold bias between the second selected column and the second selected row.
A method of simultaneously accessing a plurality of cells in an array of memory cells, comprising:
- selecting a plurality of columns;
- selecting a plurality of rows;
- simultaneously applying respective access biases between each selected column and each selected row to cause one of a write operation, an erase operation or a read operation to occur on each of the plurality of memory cells.
A method of simultaneously accessing a plurality of cells in an array of memory cells, comprising:
- selecting a plurality of columns;
- selecting a plurality of rows;
- simultaneously applying respective access biases between each selected column and each selected row, wherein simultaneously applying respective access biases comprises selecting each cell disposed between a unique selected column and a unique selected row, and wherein the unique selected column and row are not used to access other selected cells.
Dependencies are inferred from the claim text.