Driver for semiconductor memory and system including the same

A system comprising:

• a memory comprising a driver;
• an I/O interface used by a user to generate information;
• a wireless interface configured to exchange information with a wireless communication network;
• and
• a CPU configured to control the memory, the I/O interface, and the wireless interface,
• wherein the driver comprising:
• a momentarily dropping voltage generation circuit configured to generate a momentarily dropping voltage using first data for adjusting a height of an overdrive current that flows into a cell of a memory cell array and second data for adjusting a width of the overdrive current;
• a digital/analog (D/A) conversion circuit configured to output a first spike current that includes the overdrive current using the momentarily dropping voltage;
• a cell voltage detection circuit configured to compare a cell voltage to a predetermined reference voltage, and to output a comparison signal representing the comparison result, the cell voltage being generated based on a second spike current that flows into a cell of a test cell array;
• a calibration controller configured to calibrate the height and width of the overdrive current using the comparison signal output from the cell voltage detection unit;
• and
• a calibration table storage configured to store the first data for adjusting the height of the overdrive current and the second data for adjusting the width of the overdrive current,
• wherein the test cell array is arranged to correspond to the memory cell array.

A driver for a semiconductor memory, the driver comprising:

• a digital/analog (D/A) conversion circuit configured to output a spike current that includes a target current and an overdrive current, the overdrive current having a height and a width;
• a memory cell array including a cell into which the spike current flows to write data in the cell;
• and
• a spike current control circuit configured to receive height adjusting data and width adjusting data and control the height and width of the overdrive current,
• wherein the spike current control circuit includes:
• a D/A converter configured to convert the height adjusting data into an analog current;
• a height adjusting capacitor configured to receive the analog current and be charged to a charging voltage, a level of the charging voltage being determined based on the height of the overdrive current;
• a short pulse generator configured to generate a short pulse signal based on the width adjusting data, a turn-on time of the short pulse signal being determined based on the width of the overdrive current;
• and
• a width adjusting switch configured to couple the height adjusting capacitor to a gate terminal of a dropping voltage transmission switch in response to the short pulse signal.