Memory sense amplifiers and memory verification methods

A memory sense amplifier comprising:

• a first input coupled with a memory element of a memory cell, wherein the memory element has different memory states at different moments in time:
• a second input configured to receive a reference signal;
• modification circuitry configured to provide a data signal at the first input from the memory element having a plurality of different voltages corresponding to respective ones of the different memory states of the memory element at the different moments in time;
• comparison circuitry coupled with the modification circuitry and configured to compare the data signal and the reference signal at the different moments in time and to provide an output signal indicative of the memory states of the memory element at the different moments in time as a result of the comparison to implement a plurality of verify operations of the memory states of the memory element at the different moments in time;
• and
• wherein the modification circuitry comprises parallel cascode transistors individually coupled with one of the first and second inputs, and further comprising supply circuitry configured to provide different voltage biases to a gate of one of the cascode transistors to provide the data signal having the different voltages.

A memory sense amplifier comprising:

• a first input coupled with a memory element of a memory cell, wherein the memory element has different memory states at different moments in time;
• a second input configured to receive a reference signal;
• modification circuitry configured to provide a data signal at the first input from the memory element having a plurality of different voltages corresponding to respective ones of the different memory states of the memory element at the different moments in time;
• comparison circuitry coupled with the modification circuitry and configured to compare the data signal and the reference signal at the different moments in time and to provide an output signal indicative of the memory states of the memory element at the different moments in time as a result of the comparison to implement a plurality of verify operations of the memory states of the memory element at the different moments in time;
• and
• wherein the modification circuitry comprises parallel cascode transistors individually coupled with one of the first and second inputs, and further comprising supply circuitry configured to provide a first voltage bias to one of the cascode transistors corresponding to a first of the different memory states and to provide a second voltage bias to the one of the cascode transistors corresponding to a second of the different memory states.

A memory verification method comprising:

• accessing a plurality of target data values indicative of a plurality of memory states of the memory cell at different moments in time;
• accessing a data signal from the memory cell at the different moments in time;
• modifying the data signal differently corresponding to respective ones of the different memory states of the memory cell at the different moments in time;
• and
• using the modified data signal, verifying the memory states of the memory cell at the different moments in time.

A memory verification method comprising:

• accessing one of a plurality of target data values to be written to a memory cell;
• attempting to write the one target data value to the memory cell;
• and
• using the one target data value, performing a verification operation of a memory state of the memory cell comprising:
• accessing a data signal from the memory cell;
• selecting one of a plurality of modifications of the data signal corresponding to the one target data value;
• converting the data signal using the one modification;
• and
• using the modified data signal, determining whether the memory state of the memory cell corresponds to the one target data value.