Semiconductor memory device and control method thereof

A test device for testing a semiconductor memory device,

• the semiconductor memory device comprising:
• a plurality of first lines disposed in a first direction perpendicular to a main surface of a substrate and extending in a second direction parallel to the main surface of the substrate;
• a plurality of second lines disposed in the second direction and extending in the first direction, the plurality of second lines intersecting the plurality of first lines;
• a plurality of memory cells disposed at intersections of the plurality of first lines and the plurality of second lines and including a variable resistance element;
• a third line extending in a third direction orthogonal to the first direction and the second direction;
• and
• a select transistor connected between the second line and the third line,
• the test device comprising:
• a detection unit that set at least one of a plurality of the select transistors to a conductive state and thereby detects a current flowing in the third line;
• a determination unit that determines a deterioration state of the select transistor according to a result of detection;
• and
• a control unit,
• wherein
• the control unit, after a setting operation or a resetting operation on the memory cell, determines whether desired data has been written in the setting operation or the resetting operation or not, and
• the control unit, depending on a result of determination, starts in the semiconductor memory device an operation that determines the deterioration state of the select transistor.