Pseudo dual port memory using a dual port cell and a single port cell with associated valid data bits and related methods

A dual port static random access memory (SRAM) comprising:

• a pseudo dual port memory core comprising a matrix of memory cells coupled in rows and columns including
• a set of dual port memory cells configured to store data words in each of a plurality of addressed locations, and
• a set of single port memory cells configured to store data words in each of a plurality of addressed locations;
• a valid data storage unit configured to store valid bits corresponding to the addressed locations of the set of dual port memory cells and the set of single port memory cells;
• and
• control circuitry, in connection with the row decoder and column decoder, configured to access the addressed locations of the set of dual port memory cells and the set of single port memory cells by
• performing a simultaneous write operation at respective addressed locations of the set of dual port memory cells and the set of single port memory cells, and updating corresponding valid bits in the valid data storage unit, and
• performing a parallel read operation, at a same addressed location of the set of dual port memory cells and the set of single port memory cells, and determining which stored data word is valid based upon the corresponding valid bits in the valid data storage unit.

A method of implementing a pseudo dual port memory, the method comprising:

• addressing locations in a set of dual port memory cells having a read port and a write port, and in a set of single port memory cells having a read/write port, to store data words therein;
• storing valid bits, corresponding to the addressed locations of the set of dual port memory cells and the set of single port memory cells in a valid data storage unit;
• and
• accessing, with control circuitry, the addressed locations of the set of dual port memory cells and the set of single port memory cells by
• performing a simultaneous write operation using the write port of the set of dual port memory cells and the read/write port of the set of single port memory cells, and updating corresponding valid bits in the valid data storage unit, and
• performing a parallel read operation, at a same addressed location of the set of dual port memory cells and the set of single port memory cells, using the read port of the set of dual port memory cells and the read/write port of the set of single port memory cells, and determining which stored data word is valid based upon the corresponding valid bits in the valid data storage unit.