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US 9,311,989 B2Granted
Power gate for latch-up prevention
AssigneeTexas Instruments Incorporated
InventorSrinivasa Raghavan Sridhara
Life of this patent
Estimating the term…
Abstract
In an embodiment of the invention, power is provided to an SRAM array without causing latch-up by charging the positive voltage node in the SRAM array and the Nwell regions in the SRAM at approximately the same rate.
Claims6
A circuit for providing power to a static random access memory (SRAM) array without causing latch-up comprising:
- a first PFET, the first PFET having a source, a drain and a gate wherein the drain of the first PFET is connected to a positive voltage node in the SRAM array, the source of the first PFET is connected to a first power supply and the gate of the first PFET is connected to a first control signal;
- a second PFET, the second PFET having a source, a drain and a gate wherein the drain of the second PFET is connected to at least one Nwell in the SRAM array, the source of the second PFET is connected to a second power supply and the gate of the second PFET is connected to the first control signal;
- and
- a third PFET, the third PFET having a source, a drain and a gate wherein the drain of the third PFET is connected to the least one Nwell in the SRAM array, the source of the third PFET is connected to the positive voltage node in the SRAM array and the gate of the third PFET is connected to a second control signal.
1 more element
A circuit for providing power to a static random access memory (SRAM) array without causing latch-up comprising:
- a first PFET, the first PFET having a source, a drain and a gate wherein the drain of the first PFET is connected to a positive voltage node in the SRAM array, the source of the first PFET is connected to a first power supply and the gate of the first PFET is connected to a first control signal;
- a second PFET, the second PFET having a source, a drain and a gate wherein the drain of the second PFET is connected to all Nwells in the SRAM array, the source of the second PFET is connected to a second power supply and the gate of the second PFET is connected to the first control signal;
- and
- a third PFET, the third PFET having a source, a drain and a gate wherein the drain of the third PFET is connected to all Nwells in the SRAM array, the source of the third PFET is connected to the positive voltage node in the SRAM array and the gate of the third PFET is connected to a second control signal.
1 more element
Dependencies are inferred from the claim text.