I/O pin capacitance reduction using TSVs

A system, comprising:

• a selected memory die of a plurality of stacked die;
• and
• one or more unselected die of the plurality of stacked die, each of the one or more unselected die shares a vertical electrical connection with an input path of a first off-chip driver located on the selected memory die, the selected memory die configured to set a first adjustable delay for a first delay line that drives the first off-chip driver based on a location of the selected memory die within the plurality of stacked die.

An apparatus, comprising:

• a first die;
• and
• a second die located above the first die, the first die includes a first off-chip driver and the second die includes a second off-chip driver, the first die includes a first pre-driver that is in a first input signal path of the first off-chip driver, the first pre-driver connects to a second input signal path of the second off-chip driver via a vertical electrical connection between the first die and the second die, the vertical electrical connection includes a TSV that extends vertically through a substrate of the second die, the first off-chip driver drives a first output and the second off-chip driver drives the first output.