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US 9,311,978 B2Granted
Regulated power gating for growable memory
AssigneeGlobalfoundries Inc.
InventorsHarold Pilo, Richard S. Wu
Life of this patent
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Abstract
A circuit for an integrated circuit power gating system includes a header device connected to a bank of a segmented memory array. The circuit is structured and arranged to: apply a ground input to a gate of the header device to activate the bank, and apply a regulated voltage to the gate of the header device to deactivate the bank. The circuit also includes a precharge circuit that charges the gate of the header device to a precharge voltage that is greater than ground and less than the regulated voltage.
Claims16
A circuit for an integrated circuit power gating system, the circuit comprising:
- a header device connected to a bank of a segmented memory array, wherein the circuit is structured and arranged to:
- apply a ground input to a gate of the header device to activate the bank, and apply a regulated voltage to the gate of the header device to deactivate the bank;
- and
- a precharge circuit that charges the gate of the header device to a precharge voltage that is greater than ground and less than the regulated voltage,
- wherein the circuit is connected to a bus at the regulated voltage;
- and
- the circuit applies the regulated voltage to the gate of the header device by shunting the gate of the header device to the bus.
4 more elements
An integrated circuit power gating system, comprising:
- a segmented memory array comprising a plurality of banks;
- a respective header circuit associated with each respective one of the plurality of banks;
- and
- a common bus connected to each said respective header circuit,
- wherein each said respective header circuit comprises a header device connected to an associated one of the plurality of banks;
- each said respective header circuit is structured and arranged to:
- apply a ground input to a gate of the header device to activate the associated one of the plurality of banks, and apply a regulated voltage to the gate of the header device to deactivate the associated one of the plurality of banks;
- each said respective header circuit comprises a precharge circuit that charges the gate of the header device to a precharge voltage that is greater than ground and less than the regulated voltage;
- and
- the header circuit applies the regulated voltage to the gate of the header device by shunting the gate of the header device to the common bus.
7 more elements
An integrated circuit power gating system, comprising:
- a segmented memory array comprising a plurality of banks;
- a respective header circuit associated with each respective one of the plurality of banks;
- a common bus connected to each said respective header circuit;
- and
- a control circuit that generates a regulated voltage on the common bus,
- wherein each said respective header circuit comprises a header device connected to an associated one of the plurality of banks;
- each said respective header circuit is structured and arranged to:
- apply a ground input to a gate of the header device to activate the associated one of the plurality of banks, and apply the regulated voltage to the gate of the header device to deactivate the associated one of the plurality of banks;
- each said respective header circuit comprises a precharge circuit that charges the gate of the header device to a precharge voltage that is greater than ground and less than the regulated voltage;
- and
- the control circuit comprises a reference voltage generator, an operational amplifier, and a scaled header device.
8 more elements
An integrated circuit power gating system, comprising:
- a segmented memory array comprising a plurality of banks;
- a respective header circuit associated with each respective one of the plurality of banks;
- and
- a tracking array integrated with one of the plurality of banks,
- wherein each said respective header circuit comprises a header device connected to an associated one of the plurality of banks;
- each said respective header circuit is structured and arranged to:
- apply a ground input to a gate of the header device to activate the associated one of the plurality of banks, and apply a regulated voltage to the gate of the header device to deactivate the associated one of the plurality of banks;
- each said respective header circuit comprises a precharge circuit that charges the gate of the header device to a precharge voltage that is greater than ground and less than the regulated voltage;
- and
- the tracking array is smaller than the one of the plurality of banks by a predefined scale factor.
7 more elements
A method of power gating in an integrated circuit, comprising:
- precharging a gate of a header device connected to a bank of a segmented memory array prior to applying a regulated voltage to the gate of the header device, wherein the precharging raises the gate of the header device to a voltage level greater than ground and less than the regulated voltage;
- and
- shunting the gate of the header device to a bus maintained at the regulated voltage after the precharging.
Dependencies are inferred from the claim text.