Event controlled decoding circuit
AssigneeSTMicroelectronics Asia Pacific Pte Ltd
InventorBeng-Heng Goh
Life of this patent
Estimating the term…
Abstract
A waveform generator circuit includes a memory with address locations storing output waveform defining data bits. An address counter generates an address for sequentially addressing the address locations in the memory. The memory responds by sequentially outputting the output waveform defining data bits at the addressed locations. An output circuit receives the waveform defining data bits output from the memory and operates to generate an output signal waveform having logic state values dependent on the sequentially output waveform defining data bits.
Claims23
A circuit, comprising:
- an output circuit configured to receive data bits and generate an output signal waveform having logic state values dependent on the received data bits;
- a time counter configured to increment in response to a clock signal;
- a memory having a plurality of address locations, each address location storing a signal transition time linked to said data bits for that signal transition time, said memory outputting the data bits when the address location is addressed;
- a comparator configured to compare a counter value output from the time counter to the signal transition times stored in said memory and generate an increment signal in response to each comparison match;
- and
- an address counter configured to generate an address for addressing said address locations in the memory, said address counter incrementing the address in response to the increment signal at each instance of a comparison match.
A circuit, comprising:
- a time counter configured to count a current time value;
- a memory having a plurality of address locations, each address location storing a signal transition time value, wherein each transition time value is linked to data bits which define logic state values of an output signal waveform;
- a comparator configured to compare current time value to the signal transition time values stored in said memory and generate an increment signal in response to each comparison match;
- an address counter configured to generate an address for addressing said address locations in the memory, said address counter incrementing the address in response to the increment signal, wherein said memory outputs the data bits at the addressed location in the memory;
- and
- an output circuit configured to receive the output data bits and generate the output signal waveform having logic state values dependent on said output data bits.
A circuit, comprising:
- a memory having a plurality of address locations, each address location storing output data bits which define logic state values of an output signal waveform and a signal transition time value specifying a time for sequential output;
- a comparator configured to compare a current time value to the signal transition time values stored in said memory and generate an increment signal in response to each comparison match;
- an address counter configured to generate an address for sequentially addressing said address locations in the memory and increment the address in response to the increment signal, wherein said memory sequentially outputs the data bits at the addressed locations in the memory;
- and
- an output circuit configured to receive the sequentially output data bits from the memory and generate the output signal waveform having logic state values dependent on said sequentially output data bits.
Dependencies are inferred from the claim text.