Bi-synchronous electronic device and FIFO memory circuit with jump candidates and related methods

A first-in-first-out (FIFO) memory circuit to be coupled in a bi-synchronous electronic device comprising a first digital circuit operating based upon a first clock signal, and writing to the FIFO memory circuit based upon a write pointer, and a second digital circuit operating based upon a second clock signal different from the first clock signal, and reading from the FIFO memory circuit based upon a read pointer, the FIFO memory circuit comprising:

• processing circuitry, and a memory core coupled to said processing circuitry and configured to
• store data for transfer from the first digital circuit to the second digital circuit,
• detect a jump in the write pointer to a new position,
• determine a plurality of jump candidates for the read pointer from a current position,
• select a jump candidate from the plurality thereof, and
• synchronize the read pointer based upon the selected jump candidate.

A method of operating a bi-synchronous electronic device comprising a first-in-first-out (FIFO) memory circuit, the method comprising:

• using a first digital circuit coupled to the FIFO memory circuit to
• operate based upon a first clock signal, and
• write to the FIFO memory circuit based upon a write pointer;
• using a second digital circuit coupled to the FIFO memory circuit to
• operate based upon a second clock signal different from the first clock signal, and
• read from the FIFO memory circuit based upon a read pointer;
• and
• using the FIFO memory circuit to
• detect a jump in the write pointer to a new position,
• determine a plurality of jump candidates for the read pointer from a current position,
• select a jump candidate from the plurality thereof, and
• synchronize the read pointer based upon the selected jump candidate.