Input buffer for semiconductor memory device and flash memory device including the same

A flash memory device, comprising:

• a clock buffer configured to buffer a clock signal from a memory controller;
• a command buffer configured to buffer a command signal;
• an address buffer configured to buffer an address signal;
• and
• a data buffer configured to buffer a data signal,
• wherein at least one of the clock buffer, the command buffer, the address buffer and the data buffer includes,
• an amplifier circuit configured to amplify an input signal and output an amplified signal to a first output node, the input signal being amplified according to a first bias voltage set, at a bias node, to a first level based on a power supply voltage and a reference voltage,
• an output circuit configured to receive and buffer the amplified signal and output an output signal to a second output node, and
• a dynamic bias voltage generator configured to change the first bias voltage to a second level in response to a transition of the output signal.

An input buffer, comprising:

• at least one amplifier configured output an amplified signal to an output node, the amplified signal being amplified according to a bias voltage set, at a bias node, based on a power supply signal, an input signal, a reference signal, and a filtered signal, the input signal having a first phase, the amplified signal having a second phase opposite to the first phase;
• an output circuit configured to invert the amplified signal to output an output signal having the first phase;
• and
• a filter circuit configured to apply the filtered signal to the at least one amplifier by filtering a component of the output signal.