Systems and methods of semiconductor memory devices including features of output buffer initialization circuit(s) and/or multiple power-up detection/handling

A semiconductor device comprising:

• a memory cell array having a plurality of memory cells arranged in a matrix of rows and columns;
• power circuitry that provides power to the device upon power up, the power circuitry comprising a first power up circuit that outputs a first power up signal and a second power up circuit that outputs a second power-up signal, wherein the second power up circuit includes a latching circuit;
• an output buffer that outputs data from the memory cells or an output buffer pad sourced data selectively by a first control signal, wherein the output buffer includes level shifting circuitry;
• and
• a DQ pull-down level shift circuit including a first transistor coupled to ground and configured, during a power up mode when other circuitry within the pull-down level shift circuit powered by the first power up circuit has not been powered, to initialize a first cross coupled output of a cross-coupled pair of transistors too high to avoid an initial high signal on a second cross couple output, providing a signal to turn off a transistor and provide a pull down signal at a signal output.

A semiconductor device comprising:

• a memory cell array having a plurality of memory cells arranged in a matrix of rows and columns;
• power circuitry that provides power to the device upon power up, the power circuitry comprising a first power up circuit that outputs a first power up signal and a second power up circuit that outputs a second power-up signal, wherein the second power up circuit includes a latching circuit;
• an output buffer that outputs data from the memory cells or an output buffer pad sourced data selectively by a first control signal, wherein the output buffer includes level shifting circuitry;
• and
• a first PMOS transistor with first terminal connected to a power supply voltage, gate connected to the second power up signal, and second terminal connected to a signal output, a second PMOS transistor with first terminal connected to the power supply voltage, second terminal connected to the signal output, and gate connected to an earlier node of the second cross-coupled pair, two NMOS transistors in series with the second PMOS transistor with a terminal of the first NMOS transistor coupled to the signal output, and another NMOS transistor with first terminal connected to a node of the second cross-coupled pair, second terminal connected to ground, and a gate coupled to the second power up signal.

A semiconductor device comprising:

• a memory cell array having a plurality of memory cells arranged in a matrix of rows and columns;
• power circuitry that provides power to the device upon power up, the power circuitry comprising a first power up circuit that outputs a first power up signal and a second power up circuit that outputs a second power-up signal, wherein the second power up circuit includes a latching circuit;
• and
• an output buffer that outputs data from the memory cells or an output buffer pad sourced data selectively by a first control signal, wherein the output buffer includes level shifting circuitry;
• and
• wherein the output buffer comprises:
• a first group register that receives the memory cell data, the first group register generating a first set output data base on a first clock signal, a first data signal, a first enable sourced signal, and a first circuit output;
• a second group register that receives the output buffer pad sourced data and generates a second set output data base on a second clock signal, and second data signal;
• a data determination circuit having an input set signal receiving and selecting either the first set output data or the second set output data in response to the first control sourced signal, and wherein a first enabled signal is coupled to the data determination circuit to produce a first set pre-output through a first buffered set driver.