Read tracking mechanism
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsHyun-Sung Hong, Atul Katoch
Life of this patent
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Abstract
A read time tracking mechanism (RTTM) for ensuring sufficient read time is provided. The read time tracking mechanism includes a read tracking circuit, which includes a tracking bit line (TBL) tracking circuit with one or more tracking cells, and a tracking word line (TWL). The RTTM also includes a sense amplifier enable (SAE) timing device configured to change the logic threshold of tracking WL (TWL) to delay the timing of signal change of TWL when necessary to ensure sufficient read time. The read time tracking mechanism is used to provide sufficient read time for memory arrays with various configurations, prepared under various process conditions, and operated under various voltages, and temperatures.
Claims20
A read tracking circuit for a memory array, comprising:
- a tracking word line (TWL), wherein the TWL is connected to a first plurality of loading memory cells;
- a tracking bit line (TBL), wherein the TBL is connected to a tracking cell and a second plurality of loading memory cells, wherein the TWL is electrically connected to the tracking cell;
- and
- a sense amplifier enable (SAE) timing device, wherein the TWL and the TBL are connected to the SAE timing device, wherein the SAE timing device comprises:
- a logic threshold adjustment device,
- a logic NOR device, and
- a sense amplifier enable (SAE) generator.
A semiconductor memory array, comprising:
- a segment having two memory banks, wherein each of the two memory banks includes a plurality of memory cells arranged in rows and columns;
- a read tracking circuit for a memory array, comprising:
- a tracking word line (TWL), wherein the TWL is connected to a first plurality of loading memory cells;
- a tracking bit line (TBL), wherein the TBL is connected to a tracking cell and a second plurality of loading memory cells, wherein the TWL is electrically connected to the tracking cell;
- and
- a sense amplifier enable (SAE) timing device, wherein the TWL and the TBL are connected to the SAE timing device, wherein the SAE timing device comprises:
- a logic threshold adjustment device,
- a logic NOR device, and
- a sense amplifier enable (SAE) generator.
A read timing tracking method of a memory array, comprising:
- starting a tracking clock to generate a read clock signal;
- sending the read clock signal to a tracking word line (TWL) driver to generate a tracking word line (TWL) signal;
- sending the generated TWL signal to a TWL, wherein the TWL has a first plurality of loading memory cells;
- generating a tracking bit line (TBL) signal using an output signal of the TWL, wherein a TBL is coupled to at least one tracking cell and a second plurality of loading memory cells;
- sending the output signal of the TWL to a sense amplifier enable (SAE) timing device;
- sending an output signal of the TBL to the SAE timing device;
- generating an SAE signal using the SAE timing device based on the output signal of the TWL and the output signal of the TBL, wherein the SAE timing device adjusts a logic threshold of the TWL.
Dependencies are inferred from the claim text.