Configurable voltage reduction for register file

A method for operating a memory, wherein the memory includes a plurality of memory cells, the method comprising:

• generating a first voltage level of a plurality of alternative power supply voltage levels, wherein generating the first voltage level of the plurality of alternative power supply voltage levels comprises coupling a first transistor between a power supply and a power terminal on each of the plurality of memory cells, wherein a voltage level of a first control signal coupled to the first transistor is configured to turn the first transistor partially on;
• generating a second voltage level of the plurality of alternative power supply voltage levels, wherein generating the second voltage level of the plurality of alternative power supply voltage levels comprises coupling a second transistor between the power supply and an intermediate node, and coupling a third transistor between the intermediate node and the power terminal on each of the plurality of memory cells, wherein a control terminal of the second transistor is coupled to a ground reference and a control terminal of the third transistor is coupled to a second control signal;
• generating a third voltage level of the plurality of alternative power supply voltage levels, wherein generating the third voltage level of the plurality of alternative power supply voltage levels comprises decoupling the power supply from the power terminal of each memory cell of the plurality of memory cells for a duration of the operation;
• selecting one of the plurality of alternative power supply voltage levels for a level of a power supply voltage provided to each memory cell of the plurality of memory cells dependent upon one or more operating parameters;
• receiving a command, wherein the received command includes an operation to be performed on one or more of the plurality of memory cells;
• adjusting the level of the power supply voltage provided to each memory cell of the plurality of memory cells from a first voltage level to a second voltage level, wherein the second voltage level is dependent upon the selected one of the plurality of alternative power supply voltage levels;
• performing the received operation on the one or more of the plurality of memory cells;
• and
• returning the level of the power supply voltage provided to each memory cell to the first voltage level responsive to determination that the operation has completed.

A system, comprising:

• a plurality of register files, wherein each register file includes a plurality of registers;
• a plurality of power circuits, wherein each power circuit of the plurality of power circuits is coupled to a respective one of the plurality of register files, wherein each power circuit of the plurality of power circuits includes a plurality of voltage reduction circuits, and wherein each voltage reduction circuit of the plurality of voltage reduction circuits is configured to reduce a level of a power supply voltage provided to the plurality of registers in the respective one of the plurality of register files;
• and
• circuitry configured to:
• for each power circuit of the plurality of power circuits, select one voltage reduction circuit of the respective plurality of voltage reduction circuits dependent upon one or more operating parameters;
• receive a write operation directed towards one or more registers of a given register file of the plurality of register files;
• adjust the level of the power supply voltage provided to the given register file dependent upon the selected voltage reduction circuit of the respective power circuit of the plurality of power circuits;
• and
• deactivate the selected voltage reduction circuit of the respective power circuit responsive to a determination that the write operation has completed;
• wherein the plurality of voltage reduction circuits of each of the plurality of power circuits includes:
• a first voltage reduction circuit including a first transistor coupled between a power supply and a power terminal on each register of the plurality of registers of a respective one of the plurality of register files, wherein a voltage level of a first control signal coupled to the first transistor is configured to turn the first transistor partially on;
• a second voltage reduction circuit including a second transistor coupled to the power supply and an intermediate node and a third transistor coupled between the intermediate node and the power terminal on each register of the plurality of registers of the respective one of the plurality of register files, wherein a control terminal of the second transistor is coupled to a ground reference and a control terminal of the third transistor is coupled to a second control signal;
• and
• a third voltage reduction circuit configured to decouple the power supply from the power terminal on each register of the plurality of registers of the respective one of the plurality of register files for a duration of the write operation.