Processors, methods, systems, and instructions to change addresses of pages of secure enclaves

A method in a processor comprising:

• receiving a user-level instruction, the user-level instruction indicating a page of a secure enclave and indicating a linear address;
• in response to the user-level instruction, changing an initial linear address of the page of the secure enclave, which is stored in an enclave page storage metadata unit, to the linear address indicated by the user-level instruction, without losing the contents of the page of the secure enclave;
• and
• in response to the user-level instruction, configuring a hardware-implemented indicator of the processor to indicate that a secure protection mechanism associated with the page of the secure enclave is outdated, wherein configuring the hardware-implemented indicator comprises configuring one or more bits of the enclave page storage metadata unit that correspond to the page of the secure enclave.

A processor comprising:

• a hardware-implemented indicator, which is to correspond to a page of a secure enclave, and which is to be accessible to at least one user-level instruction;
• a decode unit, which includes at least some hardware of the processor, to decode a privileged-level instruction, the privileged-level instruction to indicate the page of the secure enclave;
• and
• an execution logic coupled with the decode unit, the execution logic including at least some hardware of the processor, the execution logic operable, in response to the privileged-level instruction, to:
• update a secure protection mechanism associated with the indicated page of the secure enclave;
• and
• configure the hardware-implemented indicator to indicate that the secure protection mechanism associated with the page of the secure enclave is up to date, wherein the hardware-implemented indicator is to comprise one or more bits of an enclave page storage metadata unit.

A system to process instructions comprising:

• an interconnect;
• a processor coupled with the interconnect, the processor comprising a hardware-implemented indicator, the processor to receive a user-level instruction, the user-level instruction to indicate a page of a secure enclave and the user-level instruction to indicate a linear address, the processor operable, in response to the user-level instruction, to change an initial linear address of the page of the secure enclave, which is to be stored in an enclave page storage metadata unit, to the linear address that is to be indicated by the user-level instruction, without contents of the page of the secure enclave being lost, and to configure the hardware-implemented indicator to indicate that a secure protection mechanism associated with the page of the secure enclave is outdated, wherein the hardware-implemented indicator is to comprise one or more bits of the enclave page storage metadata unit, which are to correspond to the page of the secure enclave;
• and
• a dynamic random access memory (DRAM) coupled with the interconnect.

A processor comprising:

• a die;
• a decode unit on the die to decode a user-level instruction, the user-level instruction to indicate a page of a secure enclave and the user-level instruction to indicate a linear address;
• logic of the processor on the die to prevent accesses to the page of the secure enclave from software not resident in the secure enclave including from privileged software;
• and
• an execution logic on the die and coupled with the decode unit, the execution logic operable, in response to the user-level instruction, to change an initial linear address of the page of the secure enclave, which is to be stored in an enclave page storage metadata unit, to the linear address that is to be indicated by the user-level instruction, without contents of the page of the secure enclave being lost.

A processor comprising:

• a die;
• a hardware-implemented indicator on the die, which is to correspond to a page of a secure enclave, and which is to be accessible to at least one user-level instruction;
• a decode unit on the die to decode a privileged-level instruction, the privileged-level instruction to indicate the page of the secure enclave;
• and
• logic of the processor on the die to prevent accesses to the page of the secure enclave from software not resident in the secure enclave including from privileged software;
• and
• an execution logic on the die and coupled with the decode unit, the execution logic operable, in response to the privileged-level instruction, to:
• update a secure protection mechanism associated with the indicated page of the secure enclave;
• and
• configure the hardware-implemented indicator to indicate that the secure protection mechanism associated with the page of the secure enclave is up to date.