System for processing an encrypted instruction stream in hardware
AssigneeBattelle Memorial Institute
InventorsRichard L. Griswold, William K. Nickless, Ryan C. Conrad
Life of this patent
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Abstract
A system and method of processing an encrypted instruction stream in hardware is disclosed. Main memory stores the encrypted instruction stream and unencrypted data. A central processing unit (CPU) is operatively coupled to the main memory. A decryptor is operatively coupled to the main memory and located within the CPU. The decryptor decrypts the encrypted instruction stream upon receipt of an instruction fetch signal from a CPU core. Unencrypted data is passed through to the CPU core without decryption upon receipt of a data fetch signal.
Claims41
A system for processing an encrypted instruction stream in hardware comprising:
- a. a main memory for storing the encrypted instruction stream and unencrypted data;
- b. a central processing unit (CPU) operatively coupled to the main memory via a unified instruction and data bus;
- c. a decryptor coupled to the unified instruction and data bus, wherein the decryptor decrypts the encrypted instruction stream upon receipt of an instruction fetch signal from a CPU core and wherein the decryptor passes the unencrypted data through without decryption upon receipt of a data fetch signal from the CPU core, wherein the CPU only executes instructions that have been decrypted by the CPU;
- and
- d. a boot controller for initializing the CPU to start executing the encrypted instruction stream immediately without requiring an unencrypted software boot strapping routine, wherein the CPU is initialized with only encrypted instructions that have already been encrypted off-line.
A system for processing an encrypted instruction stream in hardware comprising:
- a. a main memory for storing the encrypted instruction stream and unencrypted data;
- b. a central processing unit (CPU) operatively coupled to the main memory via a separate instruction bus and data bus;
- c. a decryptor coupled to the instruction bus but not the data bus, wherein the decryptor decrypts the encrypted instruction stream upon receipt of an instruction via the instruction bus, wherein the CPU only executes instructions that have been decrypted by the CPU;
- and
- d. a boot controller for initializing the CPU to start executing the encrypted instruction stream immediately without requiring an unencrypted software boot strapping routine, wherein the CPU is initialized with only encrypted instructions that have already been encrypted off-line.
A system for processing an encrypted instruction stream in hardware, comprising:
- a. a main memory for storing the encrypted instruction stream and unencrypted data;
- b. a central processing unit (CPU) operatively coupled to the main memory;
- c. a decryptor operatively coupled to the main memory and located within the CPU, wherein the decryptor decrypts the encrypted instruction stream upon receipt of an instruction fetch signal from a CPU core, and wherein unencrypted data is passed through to the CPU core without decryption upon receipt of a data fetch signal, wherein the CPU only executes instructions that have been decrypted by the CPU, and the instructions are encrypted off-line;
- and
- d. a boot controller for initializing the CPU to start executing the encrypted instruction stream immediately without requiring an unencrypted software boot strapping routine, wherein the CPU is initialized with only encrypted instructions that have already been encrypted off-line.
The system of 39 further comprising a data bus coupled between the CPU core and the main memory and an instruction bus coupled between the CPU core and the main memory via the decryptor, the decryptor being coupled to the instruction bus but not the data bus, wherein the decryptor decrypts the encrypted instruction stream upon receipt of an instruction via the instruction bus.
Dependencies are inferred from the claim text.