US 9,311,439 B2Granted

Methods of patterning wafers using self-aligned double patterning processes

AssigneeSamsung Electronics Co., Ltd.

InventorMoon-Gyu Jeong

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Abstract

Provided are methods of forming patterns of wafers using self-aligned double patterning processes. The methods include preparing an initial layout having a first design pattern, a second design pattern, and a third design pattern disposed between the first design pattern and the second design pattern, extracting a first sub-layout including the first design pattern and a second sub-layout including the second design pattern from the initial layout using a computer, forming a first modified sub-layout including a first modified design pattern obtained by modifying the first design pattern of the first sub-layout using the computer, generating a modified layout including the first modified sub-layout and the second sub-layout using the computer, and performing a double patterning process using the modified layout.

Claims12

Dependent claims

A method of patterning a wafer, comprising:

preparing an initial layout having a first design pattern, a second design pattern, and a third design pattern, where the third design pattern is between the first design pattern and the second design pattern, and wherein a distance between a portion of the third design pattern and a portion of one of the first design pattern and the second design pattern is less than a resolution of a photolithography apparatus;
extracting a first sub-layout that includes the first design pattern and a second sub-layout that includes the second design pattern from the initial layout;
forming a first modified sub-layout that includes a first modified design pattern obtained by modifying the first design pattern of the first sub-layout;
generating a modified layout that includes the first modified sub-layout and the second sub-layout;
generating a final layout that includes the second sub-layout and a first extended and modified sub-layout that is formed by modifying the first modified sub-layout;
forming a first photo mask that includes the second sub-layout;
using the first photo mask to form a first etching mask pattern and etching the wafer using the first etching mask as an etch mask;
forming a second photo mask that includes the first extended and modified sub-layout;
and
using the second photo mask to form a second etching mask pattern and etching the wafer using the second etching mask as an etch mask.

7 more elements

A method of patterning a wafer, comprising:

preparing an initial layout including a first design pattern, a second design pattern that extends parallel to the first design pattern, a third design pattern disposed between the first design pattern and the second design pattern, a fourth design pattern disposed between the first design pattern and the second design pattern, the third and fourth design patterns including co-linear segments that are separated by a space that is between the third design pattern and the fourth design pattern;
forming a modified layout that includes a first modified design pattern obtained by modifying the first design pattern and a second modified design pattern obtained by modifying the second design pattern, wherein the first modified design pattern includes the first design pattern and a first extra pattern that extends from the first design pattern onto the space, and the second modified design pattern includes the second design pattern and a second extra pattern that extends from the second design pattern onto the space;
forming a first photo mask that includes the first modified design pattern;
forming a second photo mask that includes the second modified design pattern and an additional pattern;
and
using the first and second photo masks in a double patterning process to pattern the wafer.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/336,155Filed 21 Jul 2014
Priority: KR 10-2014-00030739 Jan 2014
Published: US 2015/0193570 A19 Jul 2015
Granted: 12 Apr 2016
Term ends: Not estimatedThe source records don’t support an estimate.

Classification13 codes

G06F 30/39
Circuit design: circuit design at the physical level
H10P 76/00
Manufacture or treatment of masks on semiconductor bodies
G03F 7/70466
Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating…
G06F 30/398
Circuit design at the physical level: design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or…