Back to results
US 9,311,437 B2Granted
Modeling a bus for a system design incorporating one or more programmable processors
AssigneeSynopsys, Inc.
InventorsNeville A. Clark, James R. Torossian
Life of this patent
Estimating the term…
Loading patent…
Loading patent…
AssigneeSynopsys, Inc.
InventorsNeville A. Clark, James R. Torossian
Estimating the term…
Systems and methods for modeling a bus for a system design are provided. In an embodiment, the method operates by accepting a virtual bus model, wherein the model simulates behavior for a bus master and slave device, such that the model accurately simulates the timing and behavior of the transfer of data from master to slave, and, from slave to master devices. The method routes a transaction issued by the master device to the slave device. The transaction has storage for transaction data, or a pointer to transaction data, to be transferred through the transaction. The transaction data is transferred in one or more data payloads and the sender of data sets the length of data payloads to be returned. The data payloads are sent from the sender of data to the receiver of data and may contain one or more bus data beats. This method accurately models the bus timing and behavior of the delivery of one or more data beats as one data payload.
A method for processing data in a transaction through a virtual bus structure model after inclusion of the virtual bus structure model in one or more system designs including one or more programmable processors, the virtual bus structure model in the system designs located between a sender of data and a receiver of data, wherein the sender of data is configured to write data through the transaction and the receiver of data is configured to read data through the transaction, the method comprising:
A non-transitory machine readable medium containing executable instructions which when executed by a data processing system cause the system to perform operations to process data in a transaction through a virtual bus structure model after inclusion of the virtual bus structure model in one or more system designs including one or more programmable processors, the virtual bus structure model in the system designs located between a sender of data and a receiver of data, wherein the sender of data is configured to write data through the transaction and the receiver of data is configured to read data through the transaction, comprising:
A data processing system to process data in a transaction through a virtual bus structure model after inclusion of the virtual bus structure model in one or more system designs including one or more programmable processors, the virtual bus structure model in the system designs located between a sender of data and a receiver of data, wherein the sender of data is configured to write data through the transaction and the receiver of data is configured to read data through the transaction, the data processing system comprising:
Dependencies are inferred from the claim text.