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US 9,311,274 B2Granted
Approach for significant improvement of FFT performance in microcontrollers
AssigneeTexas Instruments Incorporated
InventorsProhor Chowdhury, Alexander Tessarolo
Life of this patent
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Abstract
A system includes a memory bank and a control unit. The control unit is configured to perform FFT computations based on Merged radix-2 butterfly calculations by performing FFT computations over N input items, and to access the memory bank for (½×log2N)×(10×log2N) times.
Claims12
A method, comprising:
- receiving N input items, by a control unit, from a memory bank;
- performing Fast Fourier Transform (FFT) computations, by the control unit, over the N input items, based on Merged radix-2 butterfly calculations;
- storing computed N items to the memory bank;
- and
- wherein the control unit is configured to use a Merged radix-2 butterfly calculation to process FFT calculations over four input items across two consecutive stages;
- further comprising, by the control unit, accessing the memory bank for (½×log2N)×(10×log2N) times to receive the N input items and twiddle factors, and store the N computed items.
3 more elements
A method, comprising:
- receiving N input items, by a control unit, from a memory bank;
- performing Fast Fourier Transform (FFT) computations, by the control unit, over the N input items, based on Merged radix-2 butterfly calculations;
- storing computed N items to the memory bank;
- and
- wherein the control unit is configured to use a Merged radix-2 butterfly calculation to process FFT calculations over four input items across two consecutive stages;
- further comprising, by the control unit, executing a second instruction wherein the second instruction comprises:
- performing a radix-2 butterfly calculation by reading two input items from the control unit and using a twiddle factor stored in the memory bank to generate two output butterfly values.
4 more elements
A system, comprising:
- a memory bank;
- and
- a control unit configured to perform Fast Fourier Transform (FFT) computations based on Merged radix-2 butterfly calculations by performing FFT computations over N input items, and to access the memory bank for (½×log2N)×(10×log2N) times.
A processor, comprising:
- a memory bank;
- and
- a control logic coupled to the memory bank is configured to perform Fast Fourier Transform (FFT) computations over N input items using Merged radix-2 butterfly calculations;
- wherein the control unit accesses the memory bank to retrieve input items and stores the input items in registers in the control unit for the Merged radix-2 butterfly calculations;
- and
- wherein the control unit retrieves the input items, from the registers in the control unit, for the Merged radix-2 butterfly calculations.
3 more elements
Dependencies are inferred from the claim text.