Techniques for improving throughput and performance of a distributed interconnect peripheral bus connected to a host controller

A controller apparatus, comprising:

• an accelerator configured to:
• monitor transactions to and from a host controller;
• synchronize on at least one ring assigned to a universal serial bus (USB) device, wherein the synchronizing comprises determining a pattern associated with transfer request block (TRB) address spaces of the monitored transactions;
• pre-fetch TRBs maintained in the at least one ring, wherein the TRBs are saved in a host memory based at least in part on the pattern;
• save the pre-fetched TRBs in an internal cache memory;
• receive a TRB read request from the host controller requesting a TRB;
• transfer the requested TRB from the internal cache memory to the host controller;
• and
• send a TRB read completion message to the host controller.

A non-transitory computer-readable medium having instructions executable to:

• monitor transactions to and from a host controller;
• synchronize on at least one ring assigned to a universal serial bus (USB) device, wherein the synchronizing comprises determining a pattern associated with transfer request block (TRB) address spaces of the monitored transactions;
• pre-fetch TRBs maintained in the at least one ring, wherein the TRBs are saved in a host memory based at least in part on the pattern;
• save the pre-fetched TRBs in an internal cache memory;
• receive a TRB read request from the host controller requesting a TRB;
• transfer the requested TRB from the internal cache memory to the host controller;
• and
• send a TRB read completion message to the host controller.

An apparatus for accelerating execution of read operations, comprising:

• means for monitoring transactions to and from a host controller;
• means for synchronizing on at least one ring assigned to a universal serial bus (USB) device, wherein the synchronizing comprises determining a pattern associated with transfer request block (TRB) address spaces of the monitored transactions;
• means for pre-fetching TRBs maintained in the at least one ring, wherein the TRBs are saved in a host memory based at least in part on the pattern;
• means for saving the pre-fetched TRBs in an internal cache memory;
• means for receiving a TRB read request from the host controller requesting a TRB;
• means for transferring the requested TRB from the internal cache memory to the host controller;
• and
• means for sending a TRB read completion message to the host controller.

A computing device comprising:

• an upstream bridge coupled to a host memory;
• a downstream bridge coupled to a host controller;
• and
• a controller accelerator configured to:
• monitor transactions to and from the host controller;
• synchronize on at least one ring assigned to a universal serial bus (USB) device, wherein the synchronizing comprises determining a pattern associated with transfer request block (TRB) address spaces of the monitored transactions;
• pre-fetch TRBs on the at least one ring via the upstream bridge, wherein the TRBs are saved in the host memory based at least in part on the pattern;
• save the pre-fetched TRBs in an internal cache memory;
• receive a TRB read request from the host controller via the downstream bridge requesting a TRB;
• transfer the requested TRB from the internal cache memory to the host controller via the downstream bridge;
• and
• send a TRB read completion message to the host controller via the downstream bridge.