Universal serial interface and semiconductor device including the same

A universal serial interface comprising:

• two of an inter-integrated circuit (IIC) transceiver, a universal asynchronous receiver/transmitter (UART) transceiver and a serial peripheral interface (SPI) transceiver,
• wherein the two of the IIC transceiver, the UART transceiver and the SPI transceiver are configured to share a first-in first-out (FIFO) memory,
• wherein the two of the IIC transceiver, the UART transceiver and the SPI transceiver are further configured to share a part of a special function register, and
• wherein the shared part of the special function register is configured to store a value determining a function of the FIFO memory and a value determining an on/off function of the two of the IIC transceiver, the UART transceiver and the SPI transceiver.

A universal serial interface comprising:

• two of an inter-integrated circuit (IIC) transceiver, a universal asynchronous receiver/transmitter (UART) transceiver and a serial peripheral interface (SPI) transceiver,
• wherein the two of the IIC transceiver, the UART transceiver and the SPI transceiver are configured to share a first-in first-out (FIFO) memory,
• wherein the two of the IIC transceiver, the UART transceiver and the SPI transceiver are configured to share a part of clock logic, and
• wherein the shared part of the clock logic comprises a part corresponding to a function of the FIFO memory in the clock logic.

A universal serial interface comprising:

• two of an inter-integrated circuit (IIC) transceiver, a universal asynchronous receiver/transmitter (UART) transceiver and a serial peripheral interface (SPI) transceiver,
• wherein the two of the IIC transceiver, the UART transceiver and the SPI transceiver are configured to share a first-in first-out (FIFO) memory,
• wherein the two of the IIC transceiver, the UART transceiver and the SPI transceiver are configured to share a part of interrupt logic, and
• wherein the shared part of the interrupt logic comprises a part corresponding to a function of the FIFO memory stored in the interrupt logic.

A system on chip, comprising:

• a plurality of universal serial interfaces (USIs), each of the plurality of USIs being configured to support a plurality of serial communication standards;
• and
• a central processing unit (CPU) configured to generate a configuration signal to set each of the USIs to communicate with a peripheral device using one of the supported plurality of serial communication standards, according to a serial communication standard by which the peripheral device is configured to communicate,
• wherein each of the USIs comprises:
• two transceivers configured to separately support the plurality of serial communication standards;
• a buffer configured to store received data and data to be transmitted;
• and
• a transceiver controller configured to select one of the two transceivers based on the configuration signal and connect only the selected transceiver to the buffer.