US 9,311,250 B2Granted

Techniques for memory de-duplication in a virtual system

AssigneeIntel Corporation

InventorsAdriaan Van De Ven, Keith Packard

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Abstract

Techniques for memory de-duplication in a virtual system are described. An apparatus may comprise a first processor circuit coupled to a second processor circuit. A memory unit may be coupled to the first processor circuit and the second processor circuit, the memory unit to store private memory pages and shared memory pages for multiple virtual machines. A memory management application may be operative on the first processor circuit and the second processor circuit in a shared manner to perform memory de-duplication operations on the private memory pages stored in the memory unit to form shared memory pages. The memory management application may perform sequential memory de-duplication operations on the first processor circuit, and parallel memory de-duplication operations on the second processor circuit. Other embodiments are described and claimed.

Claims19

Dependent claims

An apparatus, comprising:

a first processor circuit;
a second processor circuit coupled to the first processor circuit;
a memory unit coupled to the first processor circuit and the second processor circuit, the memory unit to store private memory pages and shared memory pages for multiple virtual machines;
a memory management application operative on the first processor circuit and the second processor circuit to perform memory de-duplication operations on the private memory pages stored in the memory unit to form shared memory pages, the memory management application to perform sequential memory de-duplication operations on the first processor circuit and parallel memory de-duplication operations on the second processor circuit, the first processor circuit capable of executing a sequential operation more quickly than the second processor circuit, and the second processor circuit capable of executing a parallel operation more quickly than the first processor circuit;
a page nomination component operative on the first processor circuit to nominate a set of candidate memory pages suitable for a shared memory page based on a set of selection criteria as at least one of the sequential memory de-duplication operations;
a page compare component operative on the second processor circuit to compare a characteristic of at least two of the candidate memory pages to identify identical memory pages as at least one of the parallel memory de-duplication operations;
and
a last level cache coupled to the first processor circuit and the second processor circuit, the page nomination component to provide indications of the candidate memory pages to the second processor circuit via the last level cache, and the page compare component to provide indications of the identical memory pages to the first processor circuit via the last level cache.

5 more elements

A computer-implemented method, comprising:

executing, by a first processor circuit, a set of sequential memory de-duplication instructions to convert a set of private memory pages into a shared memory page for multiple virtual machines;
executing, by a second processor circuit, a set of parallel memory de-duplication instructions to convert the set of private memory pages into the shared memory page for the multiple virtual machines, the first processor circuit capable of executing a sequential operation more quickly than the second processor circuit, and the second processor circuit capable of executing a parallel operation more quickly than the first processor circuit;
nominating, by the first processor circuit executing the set of sequential memory de-duplication instructions, a set of candidate memory pages suitable for the shared memory page based on a set of selection criteria;
providing, by the first processor circuit executing the set of sequential memory de-duplication instructions, indications of the set of candidate memory pages to the second processor circuit via a last level cache coupled to the first and second processor circuits;
comparing, by the second processor circuit executing the set of parallel memory de-duplication instructions, a characteristic of at least two of the candidate memory pages to identify identical memory pages;
and
providing, by the second processor circuit executing the set of parallel memory de-duplication instructions, indications of the identical memory pages to the first processor circuit via the last level cache.

4 more elements

At least one non-transitory computer-readable storage medium comprising instructions that, when executed, cause a system to:

perform, by a first processor circuit, a set of sequential memory de-duplication operations to convert multiple private memory pages for multiple virtual machines into a shared memory page for the multiple virtual machines;
perform, by a second processor circuit, a set of parallel memory de-duplication operations to convert the multiple private memory pages for the multiple virtual machines into the shared memory page for the virtual machines, the first processor circuit having a sequential processing architecture, and the second processor circuit having a parallel processing architecture;
nominate, by the first processor circuit performing the set of sequential memory de-duplication operations, a set of candidate memory pages suitable for the shared memory page based on a set of selection criteria;
provide, by the first processor circuit performing the set of sequential memory de-duplication operations, indications of the set of candidate memory pages to the second processor circuit via a last level cache coupled to the first and second processor circuits;
compare, by the second processor circuit performing the set of parallel memory de-duplication operations, a characteristic of at least two of the candidate memory pages to identify identical memory pages;
and
provide, by the second processor circuit performing the set of parallel memory de-duplication operations, indications of the identical memory pages to the first processor circuit via the last level cache.

4 more elements

Dependencies are inferred from the claim text.