Emulated message signaled interrupts in multiprocessor systems

A method, comprising:

• associating a memory address with an input/output (I/O) device in a multiprocessor system;
• reserving a first cache line of an interrupt reserved portion of a first cache memory of a first processor for interrupt handling and mapping the first cache line to the memory address assigned to a first message signaled interrupt from the I/O device;
• reserving a second cache line of a second cache memory of a second processor for interrupt handling and mapping the second cache line to the memory address;
• initializing a coherency state of the first cache line and the second cache line to a shared coherency state;
• responsive to detecting an I/O transaction containing I/O data from the I/O device and indicating a target address selected from:
• a direct address of the first cache line, a direct address of the second cache line, and the memory address:
• storing the I/O data in the memory address, the first cache line, and the second cache line;
• transitioning the coherency state of the first cache line from the shared coherency state to an in-use coherency state, wherein the in-use coherency state is to indicate that an interrupt service routine corresponding to the first message signaled interrupt is in execution;
• emulating, by the first processor, a first emulated message signaled interrupt (MSI) referencing the memory address responsive to storing the I/O data in the first cache line;
• and
• emulating, by the second processor, a second emulated MSI referencing the memory address responsive to storing the I/O data in the second cache line.

A computer system, comprising:

• first storage to store input/output (I/O) configuration data to indicate a memory address associated with an I/O device;
• a processor;
• an I/O device coupled to the processor;
• the processor including:
• a first core;
• a first cache memory;
• and
• a cache controller to:
• set an interrupt reserved indicator of a first cache line of an interrupt reserved portion of the first cache memory for message signaled interrupt processing;
• map the first cache line to a memory address associated with the I/O device and assigned to a first message signaled interrupt from the I/O device;
• set a coherency state of the first cache line to shared;
• write I/O data of an I/O transaction from the I/O device to the first cache line;
• transition the coherency state of the first cache line from the shared coherency state to an in-use coherency state, wherein the in-use coherency state is to indicate that an interrupt service routine corresponding to the first message signaled interrupt is in execution;
• and
• responsive to detection of the I/O transaction from the I/O device and containing a reference to the memory address, emulate the first message signaled interrupt that identifies the memory address.