Method and apparatus to write modified cache data to a backing store while retaining write permissions
AssigneeIntel Corporation
InventorsRavi Rajwar, Robert Chappell, Zhongying Zhang, Jason Bessette
Life of this patent
Estimating the term…
Abstract
A method is described that includes performing the following for a transactional operation in response to a request from a processing unit that is directed to a cache identifying a cache line. Reading the cache line, and, if the cache line is in a Modified cache coherency protocol state, forwarding the cache line to circuitry that will cause the cache line to be written to deeper storage, and, changing another instance of the cache line that is available to the processing unit for the transactional operation to an Exclusive cache coherency state.
Claims24
A processor comprising:
- a plurality of processing cores;
- a cache communicatively coupled to the processing cores, the cache to store cache lines;
- and
- logic circuitry associated with the cache to perform the following in a same cycle in response to a request for a memory operation from one of the processing cores that is directed to a cache line in the cache:
- read the cache line from the cache, and if the cache line is in a modified cache coherency protocol state, forward a copy of the cache line to a write buffer of circuitry that is to cause the copy of the cache line to be written to deeper storage, change the cache line in the cache to an exclusive cache coherency protocol state, and perform the memory operation.
A computing system comprising:
- a plurality of processors;
- a cache communicatively coupled to the processors;
- and
- logic circuitry associated with the cache to perform the following in a same cycle in
- response to a request for a memory operation from one of the processors that is directed to a cache line in the cache:
- read the cache line from the cache, and if the cache line is in a modified cache coherency protocol state, forward a copy of the cache line to a write buffer of circuitry that is to cause the copy of the cache line to be written to deeper storage, change the cache line to an exclusive cache coherency protocol state, and perform the memory operation.
A method comprising:
- performing the following in a same cycle in response to a request for a memory operation from a processing unit that is directed to a cache line in a cache:
- reading the cache line from the cache, and if the cache line is in a modified cache coherency protocol state, forwarding a copy of the cache line to a write buffer of circuitry that is to cause the copy of the cache line to be written to deeper storage, changing the cache line in the cache to an exclusive cache coherency protocol state, and performing the memory operation.
A processor comprising:
- a plurality of processing cores;
- a cache communicatively coupled to the processing cores, the cache to store cache lines;
- and
- logic circuitry associated with the cache to perform the following in a same cycle in response to a request for a process from one of the processing cores that is directed to a cache line in the cache:
- read the cache line from the cache, and if the cache line is in a modified cache coherency protocol state, forward a copy of the cache line to a write buffer of circuitry that is to cause the copy of the cache line to be written to deeper storage, change the cache line in the cache to an exclusive cache coherency protocol state, and perform the process, wherein the process comprises at least one of:
- speculative execution,
- soft error rate reduction, and
- high performance cache cleaning.
Dependencies are inferred from the claim text.